\hypertarget{unionComSquare_1_1CPU_1_1Registers_1_1p}{}\doxysection{Com\+Square\+::C\+PU\+::Registers\+::p Union Reference}
\label{unionComSquare_1_1CPU_1_1Registers_1_1p}\index{ComSquare::CPU::Registers::p@{ComSquare::CPU::Registers::p}}


The Processor status register;.  




{\ttfamily \#include $<$C\+P\+U.\+hpp$>$}



Collaboration diagram for Com\+Square\+::C\+PU\+::Registers\+::p\+:\nopagebreak
\begin{figure}[H]
\begin{center}
\leavevmode
\includegraphics[width=243pt]{unionComSquare_1_1CPU_1_1Registers_1_1p__coll__graph}
\end{center}
\end{figure}
\doxysubsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
bool \mbox{\hyperlink{unionComSquare_1_1CPU_1_1Registers_1_1p_a79fb1e23a5513904a314fa643a5345fa}{n}}\+: 1
\begin{DoxyCompactList}\small\item\em The Negative flag. \end{DoxyCompactList}\item 
bool \mbox{\hyperlink{unionComSquare_1_1CPU_1_1Registers_1_1p_ae8da7fb7a0058a9fa21d2e561ba5483d}{v}}\+: 1
\begin{DoxyCompactList}\small\item\em The o\+Verflow flag. \end{DoxyCompactList}\item 
bool \mbox{\hyperlink{unionComSquare_1_1CPU_1_1Registers_1_1p_a62692730cec2435e0b8fa60b3f91cef2}{m}}\+: 1
\begin{DoxyCompactList}\small\item\em The accumulator and \mbox{\hyperlink{namespaceComSquare_1_1Memory}{Memory}} width flag (in native mode only) \end{DoxyCompactList}\item 
\begin{tabbing}
xx\=xx\=xx\=xx\=xx\=xx\=xx\=xx\=xx\=\kill
union \{\\
\>bool \mbox{\hyperlink{unionComSquare_1_1CPU_1_1Registers_1_1p_a3ec9f5d30896da6de362318a57d41288}{x}}: 1\\
\>\>{\em The indeX register width flag (in native mode only) }\\
\>bool \mbox{\hyperlink{unionComSquare_1_1CPU_1_1Registers_1_1p_a7f78eb7506a2e5215b4716b5ac76361c}{b}}: 1\\
\>\>{\em The Break flag (in emulation mode only) }\\
\}; \\

\end{tabbing}\item 
bool \mbox{\hyperlink{unionComSquare_1_1CPU_1_1Registers_1_1p_a6980012f88ee439133118611b8ae5700}{d}}\+: 1
\begin{DoxyCompactList}\small\item\em The Decimal mode flag. \end{DoxyCompactList}\item 
bool \mbox{\hyperlink{unionComSquare_1_1CPU_1_1Registers_1_1p_a34bc831614cb1f021f3de7e4d7d2001a}{i}}\+: 1
\begin{DoxyCompactList}\small\item\em The Interrupt disable flag. \end{DoxyCompactList}\item 
bool \mbox{\hyperlink{unionComSquare_1_1CPU_1_1Registers_1_1p_ab378733e206cf5e3609e7ad08c586f6a}{z}}\+: 1
\begin{DoxyCompactList}\small\item\em The Zero flag. \end{DoxyCompactList}\item 
bool \mbox{\hyperlink{unionComSquare_1_1CPU_1_1Registers_1_1p_a0a2e971016ff6468b4d6644e89b3e355}{c}}\+: 1
\begin{DoxyCompactList}\small\item\em The Carry flag. \end{DoxyCompactList}\end{DoxyCompactItemize}


\doxysubsection{Detailed Description}
The Processor status register;. 

\doxysubsection{Member Data Documentation}
\mbox{\Hypertarget{unionComSquare_1_1CPU_1_1Registers_1_1p_af4f787d47b8d2a76227ccf5d5437eda5}\label{unionComSquare_1_1CPU_1_1Registers_1_1p_af4f787d47b8d2a76227ccf5d5437eda5}} 
\doxysubsubsection{\texorpdfstring{"@51}{@51}}
{\footnotesize\ttfamily union \{ ... \} }

\mbox{\Hypertarget{unionComSquare_1_1CPU_1_1Registers_1_1p_a7f78eb7506a2e5215b4716b5ac76361c}\label{unionComSquare_1_1CPU_1_1Registers_1_1p_a7f78eb7506a2e5215b4716b5ac76361c}} 
\index{ComSquare::CPU::Registers::p@{ComSquare::CPU::Registers::p}!b@{b}}
\index{b@{b}!ComSquare::CPU::Registers::p@{ComSquare::CPU::Registers::p}}
\doxysubsubsection{\texorpdfstring{b}{b}}
{\footnotesize\ttfamily bool Com\+Square\+::\+C\+P\+U\+::\+Registers\+::p\+::b}



The Break flag (in emulation mode only) 

\mbox{\Hypertarget{unionComSquare_1_1CPU_1_1Registers_1_1p_a0a2e971016ff6468b4d6644e89b3e355}\label{unionComSquare_1_1CPU_1_1Registers_1_1p_a0a2e971016ff6468b4d6644e89b3e355}} 
\index{ComSquare::CPU::Registers::p@{ComSquare::CPU::Registers::p}!c@{c}}
\index{c@{c}!ComSquare::CPU::Registers::p@{ComSquare::CPU::Registers::p}}
\doxysubsubsection{\texorpdfstring{c}{c}}
{\footnotesize\ttfamily bool Com\+Square\+::\+C\+P\+U\+::\+Registers\+::p\+::c}



The Carry flag. 

\mbox{\Hypertarget{unionComSquare_1_1CPU_1_1Registers_1_1p_a6980012f88ee439133118611b8ae5700}\label{unionComSquare_1_1CPU_1_1Registers_1_1p_a6980012f88ee439133118611b8ae5700}} 
\index{ComSquare::CPU::Registers::p@{ComSquare::CPU::Registers::p}!d@{d}}
\index{d@{d}!ComSquare::CPU::Registers::p@{ComSquare::CPU::Registers::p}}
\doxysubsubsection{\texorpdfstring{d}{d}}
{\footnotesize\ttfamily bool Com\+Square\+::\+C\+P\+U\+::\+Registers\+::p\+::d}



The Decimal mode flag. 

\mbox{\Hypertarget{unionComSquare_1_1CPU_1_1Registers_1_1p_a34bc831614cb1f021f3de7e4d7d2001a}\label{unionComSquare_1_1CPU_1_1Registers_1_1p_a34bc831614cb1f021f3de7e4d7d2001a}} 
\index{ComSquare::CPU::Registers::p@{ComSquare::CPU::Registers::p}!i@{i}}
\index{i@{i}!ComSquare::CPU::Registers::p@{ComSquare::CPU::Registers::p}}
\doxysubsubsection{\texorpdfstring{i}{i}}
{\footnotesize\ttfamily bool Com\+Square\+::\+C\+P\+U\+::\+Registers\+::p\+::i}



The Interrupt disable flag. 

\mbox{\Hypertarget{unionComSquare_1_1CPU_1_1Registers_1_1p_a62692730cec2435e0b8fa60b3f91cef2}\label{unionComSquare_1_1CPU_1_1Registers_1_1p_a62692730cec2435e0b8fa60b3f91cef2}} 
\index{ComSquare::CPU::Registers::p@{ComSquare::CPU::Registers::p}!m@{m}}
\index{m@{m}!ComSquare::CPU::Registers::p@{ComSquare::CPU::Registers::p}}
\doxysubsubsection{\texorpdfstring{m}{m}}
{\footnotesize\ttfamily bool Com\+Square\+::\+C\+P\+U\+::\+Registers\+::p\+::m}



The accumulator and \mbox{\hyperlink{namespaceComSquare_1_1Memory}{Memory}} width flag (in native mode only) 

\mbox{\Hypertarget{unionComSquare_1_1CPU_1_1Registers_1_1p_a79fb1e23a5513904a314fa643a5345fa}\label{unionComSquare_1_1CPU_1_1Registers_1_1p_a79fb1e23a5513904a314fa643a5345fa}} 
\index{ComSquare::CPU::Registers::p@{ComSquare::CPU::Registers::p}!n@{n}}
\index{n@{n}!ComSquare::CPU::Registers::p@{ComSquare::CPU::Registers::p}}
\doxysubsubsection{\texorpdfstring{n}{n}}
{\footnotesize\ttfamily bool Com\+Square\+::\+C\+P\+U\+::\+Registers\+::p\+::n}



The Negative flag. 

\mbox{\Hypertarget{unionComSquare_1_1CPU_1_1Registers_1_1p_ae8da7fb7a0058a9fa21d2e561ba5483d}\label{unionComSquare_1_1CPU_1_1Registers_1_1p_ae8da7fb7a0058a9fa21d2e561ba5483d}} 
\index{ComSquare::CPU::Registers::p@{ComSquare::CPU::Registers::p}!v@{v}}
\index{v@{v}!ComSquare::CPU::Registers::p@{ComSquare::CPU::Registers::p}}
\doxysubsubsection{\texorpdfstring{v}{v}}
{\footnotesize\ttfamily bool Com\+Square\+::\+C\+P\+U\+::\+Registers\+::p\+::v}



The o\+Verflow flag. 

\mbox{\Hypertarget{unionComSquare_1_1CPU_1_1Registers_1_1p_a3ec9f5d30896da6de362318a57d41288}\label{unionComSquare_1_1CPU_1_1Registers_1_1p_a3ec9f5d30896da6de362318a57d41288}} 
\index{ComSquare::CPU::Registers::p@{ComSquare::CPU::Registers::p}!x@{x}}
\index{x@{x}!ComSquare::CPU::Registers::p@{ComSquare::CPU::Registers::p}}
\doxysubsubsection{\texorpdfstring{x}{x}}
{\footnotesize\ttfamily bool Com\+Square\+::\+C\+P\+U\+::\+Registers\+::p\+::x}



The indeX register width flag (in native mode only) 

\mbox{\Hypertarget{unionComSquare_1_1CPU_1_1Registers_1_1p_ab378733e206cf5e3609e7ad08c586f6a}\label{unionComSquare_1_1CPU_1_1Registers_1_1p_ab378733e206cf5e3609e7ad08c586f6a}} 
\index{ComSquare::CPU::Registers::p@{ComSquare::CPU::Registers::p}!z@{z}}
\index{z@{z}!ComSquare::CPU::Registers::p@{ComSquare::CPU::Registers::p}}
\doxysubsubsection{\texorpdfstring{z}{z}}
{\footnotesize\ttfamily bool Com\+Square\+::\+C\+P\+U\+::\+Registers\+::p\+::z}



The Zero flag. 



The documentation for this union was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
sources/\+C\+P\+U/\mbox{\hyperlink{CPU_8hpp}{C\+P\+U.\+hpp}}\end{DoxyCompactItemize}
