CPU.hpp
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//
// Created by anonymus-raccoon on 1/24/20.
//
#ifndef COMSQUARE_CPU_HPP
#define COMSQUARE_CPU_HPP
#include "../Memory/IMemory.hpp"
#include "../Memory/MemoryBus.hpp"
#include "../Models/Ints.hpp"
namespace ComSquare::CPU
{
struct Registers {
union {
struct {
uint8_t ah;
uint8_t al;
};
uint16_t a;
};
uint8_t dbr;
union {
struct {
uint8_t dh;
uint8_t dl;
};
uint16_t d;
};
uint8_t k;
union {
struct {
uint8_t pch;
uint8_t pcl;
};
uint16_t pc;
};
union {
struct {
uint8_t sh;
uint8_t sl;
};
uint16_t s;
};
union {
struct {
uint8_t xh;
uint8_t xl;
};
uint16_t x;
};
union {
struct {
uint8_t yh;
uint8_t yl;
};
uint16_t y;
};
union p {
bool n : 1;
bool v : 1;
bool m : 1;
union {
bool x : 1;
bool b : 1;
};
bool d : 1;
bool i : 1;
bool z : 1;
bool c : 1;
};
};
struct InternalRegisters
{
uint8_t nmitimen;
uint8_t wrio;
uint8_t wrmpya;
uint8_t wrmpyb;
uint8_t wrdivl;
uint8_t wrdivh;
uint8_t wrdivb;
uint8_t htimel;
uint8_t htimeh;
uint8_t vtimel;
uint8_t vtimeh;
uint8_t mdmaen;
uint8_t hdmaen;
uint8_t memsel;
uint8_t rdnmi;
uint8_t timeup;
uint8_t hvbjoy;
uint8_t rdio;
uint8_t rddivl;
uint8_t rddivh;
uint8_t rdmpyl;
uint8_t rdmpyh;
uint8_t joy1l;
uint8_t joy1h;
uint8_t joy2l;
uint8_t joy2h;
uint8_t joy3l;
uint8_t joy3h;
uint8_t joy4l;
uint8_t joy4h;
};
class CPU : public Memory::IMemory {
private:
Registers _registers{};
bool _isEmulationMode = true;
InternalRegisters _internalRegisters{};
std::shared_ptr<Memory::MemoryBus> _bus;
int executeInstruction();
public:
explicit CPU(std::shared_ptr<Memory::MemoryBus> bus);
int update();
uint8_t read(uint24_t addr) override;
void write(uint24_t addr, uint8_t data) override;
};
}
#endif //COMSQUARE_CPU_HPP
ComSquare::CPU::Registers::p::b
bool b
The Break flag (in emulation mode only)
Definition: CPU.hpp:81
ComSquare::CPU::InternalRegisters::joy4h
uint8_t joy4h
Controller Port Data Registers (Pad 4 - High)
Definition: CPU.hpp:173
ComSquare::CPU::Registers::sh
uint8_t sh
Definition: CPU.hpp:47
ComSquare::CPU::Registers::p::x
bool x
The indeX register width flag (in native mode only)
Definition: CPU.hpp:79
ComSquare::CPU::Registers::dl
uint8_t dl
Definition: CPU.hpp:30
ComSquare::CPU::Registers::d
uint16_t d
Definition: CPU.hpp:32
ComSquare::CPU::InternalRegisters::joy4l
uint8_t joy4l
Controller Port Data Registers (Pad 4 - Low)
Definition: CPU.hpp:171
ComSquare::CPU::Registers::p::i
bool i
The Interrupt disable flag.
Definition: CPU.hpp:86
ComSquare::CPU::Registers::yh
uint8_t yh
Definition: CPU.hpp:63
ComSquare::CPU::Registers::pc
uint16_t pc
Definition: CPU.hpp:42
ComSquare::CPU::InternalRegisters::joy3h
uint8_t joy3h
Controller Port Data Registers (Pad 3 - High)
Definition: CPU.hpp:168
ComSquare::CPU::InternalRegisters::joy3l
uint8_t joy3l
Controller Port Data Registers (Pad 3 - Low)
Definition: CPU.hpp:166
ComSquare::CPU::InternalRegisters::rdio
uint8_t rdio
IO Port Read Register.
Definition: CPU.hpp:143
ComSquare::CPU::CPU
The main CPU.
Definition: CPU.hpp:177
ComSquare::CPU::InternalRegisters::wrio
uint8_t wrio
IO Port Write Register.
Definition: CPU.hpp:101
ComSquare::CPU::InternalRegisters::vtimel
uint8_t vtimel
IRQ Timer Registers (Vertical - Low)
Definition: CPU.hpp:121
ComSquare::CPU::Registers::dbr
uint8_t dbr
The Data Bank Register;.
Definition: CPU.hpp:25
ComSquare::CPU::Registers::p::n
bool n
The Negative flag.
Definition: CPU.hpp:72
ComSquare::CPU::Registers::xh
uint8_t xh
Definition: CPU.hpp:55
ComSquare::CPU::CPU::_isEmulationMode
bool _isEmulationMode
Is the CPU running in emulation mode (in 8bits)
Definition: CPU.hpp:182
ComSquare::CPU::CPU::write
void write(uint24_t addr, uint8_t data) override
Write data to the internal CPU register.
Definition: CPU.cpp:86
ComSquare::CPU::Registers::pch
uint8_t pch
Definition: CPU.hpp:39
ComSquare::CPU::InternalRegisters::wrdivb
uint8_t wrdivb
Divisor & Dividend Registers (B)
Definition: CPU.hpp:113
ComSquare::CPU
Definition: CPU.cpp:11
ComSquare::CPU::InternalRegisters::rddivl
uint8_t rddivl
Divide Result Registers (can sometimes be used as multiplication result register) - LOW.
Definition: CPU.hpp:146
ComSquare::CPU::InternalRegisters::wrdivh
uint8_t wrdivh
Divisor & Dividend Registers (A - High)
Definition: CPU.hpp:111
ComSquare::CPU::InternalRegisters::htimel
uint8_t htimel
IRQ Timer Registers (Horizontal - Low)
Definition: CPU.hpp:116
ComSquare::CPU::InternalRegisters::joy1l
uint8_t joy1l
Controller Port Data Registers (Pad 1 - Low)
Definition: CPU.hpp:156
uint24_t
unsigned uint24_t
Definition: Ints.hpp:8
ComSquare::CPU::InternalRegisters::rdmpyl
uint8_t rdmpyl
Multiplication Result Registers (can sometimes be used as divide result register) - LOW.
Definition: CPU.hpp:151
ComSquare::CPU::Registers::p::v
bool v
The oVerflow flag.
Definition: CPU.hpp:74
ComSquare::Memory::IMemory
Common interface implemented by all components mapping memory.
Definition: IMemory.hpp:16
ComSquare::CPU::InternalRegisters::timeup
uint8_t timeup
Interrupt Flag Registers - TimeUp.
Definition: CPU.hpp:137
ComSquare::CPU::InternalRegisters::htimeh
uint8_t htimeh
IRQ Timer Registers (Horizontal - High)
Definition: CPU.hpp:118
ComSquare::CPU::CPU::executeInstruction
int executeInstruction()
Execute a single instruction.
Definition: CPU.cpp:193
ComSquare::CPU::Registers::k
uint8_t k
The program banK register;.
Definition: CPU.hpp:35
ComSquare::CPU::Registers::p::z
bool z
The Zero flag.
Definition: CPU.hpp:88
ComSquare::CPU::InternalRegisters::joy1h
uint8_t joy1h
Controller Port Data Registers (Pad 1 - High)
Definition: CPU.hpp:158
ComSquare::CPU::Registers::p
The Processor status register;.
Definition: CPU.hpp:70
ComSquare::CPU::InternalRegisters::rddivh
uint8_t rddivh
Divide Result Registers (can sometimes be used as multiplication result register) - HIGH.
Definition: CPU.hpp:148
ComSquare::CPU::CPU::read
uint8_t read(uint24_t addr) override
Read from the internal CPU register.
Definition: CPU.cpp:18
ComSquare::CPU::InternalRegisters::wrdivl
uint8_t wrdivl
Divisor & Dividend Registers (A - Low)
Definition: CPU.hpp:109
ComSquare::CPU::InternalRegisters::hvbjoy
uint8_t hvbjoy
PPU Status Register.
Definition: CPU.hpp:140
ComSquare::CPU::InternalRegisters
Struct containing internal registers of the CPU.
Definition: CPU.hpp:95
ComSquare::CPU::Registers::sl
uint8_t sl
Definition: CPU.hpp:48
ComSquare::CPU::InternalRegisters::memsel
uint8_t memsel
ROM Speed Register.
Definition: CPU.hpp:132
ComSquare::CPU::InternalRegisters::joy2l
uint8_t joy2l
Controller Port Data Registers (Pad 2 - Low)
Definition: CPU.hpp:161
ComSquare::CPU::CPU::_internalRegisters
InternalRegisters _internalRegisters
Internal registers of the CPU (accessible from the bus via addr $4200 to $421F).
Definition: CPU.hpp:184
ComSquare::CPU::InternalRegisters::mdmaen
uint8_t mdmaen
DMA Enable Register.
Definition: CPU.hpp:126
ComSquare::CPU::Registers::pcl
uint8_t pcl
Definition: CPU.hpp:40
ComSquare::CPU::InternalRegisters::nmitimen
uint8_t nmitimen
Interrupt Enable Register.
Definition: CPU.hpp:98
ComSquare::CPU::CPU::CPU
CPU(std::shared_ptr< Memory::MemoryBus > bus)
Definition: CPU.cpp:13
ComSquare::CPU::InternalRegisters::rdmpyh
uint8_t rdmpyh
Multiplication Result Registers (can sometimes be used as divide result register) - HIGH.
Definition: CPU.hpp:153
ComSquare::CPU::InternalRegisters::joy2h
uint8_t joy2h
Controller Port Data Registers (Pad 2 - High)
Definition: CPU.hpp:163
ComSquare::CPU::Registers::yl
uint8_t yl
Definition: CPU.hpp:64
ComSquare::CPU::InternalRegisters::vtimeh
uint8_t vtimeh
IRQ Timer Registers (Vertical - High)
Definition: CPU.hpp:123
ComSquare::CPU::Registers::p::d
bool d
The Decimal mode flag.
Definition: CPU.hpp:84
ComSquare::CPU::CPU::_registers
Registers _registers
All the registers of the CPU.
Definition: CPU.hpp:180
ComSquare::CPU::Registers
Struct containing registers for the main CPU.
Definition: CPU.hpp:15
ComSquare::CPU::Registers::x
uint16_t x
Definition: CPU.hpp:58
ComSquare::CPU::Registers::dh
uint8_t dh
Definition: CPU.hpp:29
ComSquare::CPU::Registers::y
uint16_t y
Definition: CPU.hpp:66
ComSquare::CPU::Registers::ah
uint8_t ah
Definition: CPU.hpp:19
ComSquare::CPU::Registers::p::m
bool m
The accumulator and Memory width flag (in native mode only)
Definition: CPU.hpp:76
ComSquare::CPU::Registers::al
uint8_t al
Definition: CPU.hpp:20
ComSquare::CPU::InternalRegisters::wrmpyb
uint8_t wrmpyb
Multiplicand Register B.
Definition: CPU.hpp:106
ComSquare::CPU::InternalRegisters::rdnmi
uint8_t rdnmi
Interrupt Flag Registers.
Definition: CPU.hpp:135
ComSquare::CPU::InternalRegisters::hdmaen
uint8_t hdmaen
HDMA Enable Register.
Definition: CPU.hpp:129
ComSquare::CPU::Registers::s
uint16_t s
Definition: CPU.hpp:50
ComSquare::CPU::Registers::p::c
bool c
The Carry flag.
Definition: CPU.hpp:90
ComSquare::CPU::CPU::update
int update()
This function continue to execute the Cartridge code.
Definition: CPU.cpp:184
ComSquare::CPU::Registers::a
uint16_t a
Definition: CPU.hpp:22
ComSquare::CPU::Registers::xl
uint8_t xl
Definition: CPU.hpp:56
ComSquare::CPU::InternalRegisters::wrmpya
uint8_t wrmpya
Multiplicand Register A.
Definition: CPU.hpp:104
ComSquare::CPU::CPU::_bus
std::shared_ptr< Memory::MemoryBus > _bus
The memory bus to use for read/write.
Definition: CPU.hpp:186