\hypertarget{structComSquare_1_1APU_1_1Registers}{}\doxysection{Com\+Square\+::A\+PU\+::Registers Struct Reference}
\label{structComSquare_1_1APU_1_1Registers}\index{ComSquare::APU::Registers@{ComSquare::APU::Registers}}


{\ttfamily \#include $<$A\+P\+U.\+hpp$>$}



Collaboration diagram for Com\+Square\+::A\+PU\+::Registers\+:\nopagebreak
\begin{figure}[H]
\begin{center}
\leavevmode
\includegraphics[width=231pt]{structComSquare_1_1APU_1_1Registers__coll__graph}
\end{center}
\end{figure}
\doxysubsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
uint8\+\_\+t \mbox{\hyperlink{structComSquare_1_1APU_1_1Registers_abdfe3b23ea43931f53f9f66b83ea9129}{unknown}}
\begin{DoxyCompactList}\small\item\em An undocumented register. \end{DoxyCompactList}\item 
uint8\+\_\+t \mbox{\hyperlink{structComSquare_1_1APU_1_1Registers_a1585ec8bcac768a022fedd51055bb880}{ctrlreg}}
\begin{DoxyCompactList}\small\item\em Control Register register. \end{DoxyCompactList}\item 
uint8\+\_\+t \mbox{\hyperlink{structComSquare_1_1APU_1_1Registers_ae047df53c9430cdf6f597fb9ff9c2cd9}{dspreg\+Addr}}
\begin{DoxyCompactList}\small\item\em \mbox{\hyperlink{namespaceComSquare_1_1APU_1_1DSP}{D\+SP}} Register Address register. \end{DoxyCompactList}\item 
uint8\+\_\+t \mbox{\hyperlink{structComSquare_1_1APU_1_1Registers_abb9147763fef0f13c5e3773efd38fe0a}{dspreg\+Data}}
\begin{DoxyCompactList}\small\item\em \mbox{\hyperlink{namespaceComSquare_1_1APU_1_1DSP}{D\+SP}} Register data register. \end{DoxyCompactList}\item 
uint8\+\_\+t \mbox{\hyperlink{structComSquare_1_1APU_1_1Registers_a7596aa3a3d238924fb36b674a5b29723}{port0}}
\begin{DoxyCompactList}\small\item\em Port 0 register. \end{DoxyCompactList}\item 
uint8\+\_\+t \mbox{\hyperlink{structComSquare_1_1APU_1_1Registers_aff7ac077d11b5cb170de27aa242d47d4}{port1}}
\begin{DoxyCompactList}\small\item\em Port 1 register. \end{DoxyCompactList}\item 
uint8\+\_\+t \mbox{\hyperlink{structComSquare_1_1APU_1_1Registers_a61577de367bc230163586c46d4959e9d}{port2}}
\begin{DoxyCompactList}\small\item\em Port 2 register. \end{DoxyCompactList}\item 
uint8\+\_\+t \mbox{\hyperlink{structComSquare_1_1APU_1_1Registers_a9661edea32acb0e434aa08cc4451a108}{port3}}
\begin{DoxyCompactList}\small\item\em Port 3 register. \end{DoxyCompactList}\item 
uint8\+\_\+t \mbox{\hyperlink{structComSquare_1_1APU_1_1Registers_a1b8880642a44bc70c8fa4703390c69e5}{regmem1}}
\begin{DoxyCompactList}\small\item\em Regular \mbox{\hyperlink{namespaceComSquare_1_1Memory}{Memory}} register. \end{DoxyCompactList}\item 
uint8\+\_\+t \mbox{\hyperlink{structComSquare_1_1APU_1_1Registers_a796c629e166e6a1dc1853b33556f83fa}{regmem2}}
\begin{DoxyCompactList}\small\item\em Another Regular \mbox{\hyperlink{namespaceComSquare_1_1Memory}{Memory}} register. \end{DoxyCompactList}\item 
uint8\+\_\+t \mbox{\hyperlink{structComSquare_1_1APU_1_1Registers_ad0c1fb4090040f8bf28ecef922f88e92}{timer0}}
\begin{DoxyCompactList}\small\item\em Timer-\/0 register. \end{DoxyCompactList}\item 
uint8\+\_\+t \mbox{\hyperlink{structComSquare_1_1APU_1_1Registers_a63d92eb8b1bcc693d7afcb587230f1d1}{timer1}}
\begin{DoxyCompactList}\small\item\em Timer-\/1 register. \end{DoxyCompactList}\item 
uint8\+\_\+t \mbox{\hyperlink{structComSquare_1_1APU_1_1Registers_a1707b3935184f283f0270526773d450b}{timer2}}
\begin{DoxyCompactList}\small\item\em Timer-\/2 register. \end{DoxyCompactList}\item 
uint8\+\_\+t \mbox{\hyperlink{structComSquare_1_1APU_1_1Registers_a0e72e8ea66b03c6a05b827a3b398f6fe}{counter0}}
\begin{DoxyCompactList}\small\item\em Counter-\/0 register. \end{DoxyCompactList}\item 
uint8\+\_\+t \mbox{\hyperlink{structComSquare_1_1APU_1_1Registers_ac8a31fa1b2989fb34f5d167edf737b15}{counter1}}
\begin{DoxyCompactList}\small\item\em Counter-\/1 register. \end{DoxyCompactList}\item 
uint8\+\_\+t \mbox{\hyperlink{structComSquare_1_1APU_1_1Registers_a888f86198d592c702cdc1c25fbe0e3f5}{counter2}}
\begin{DoxyCompactList}\small\item\em Counter-\/2 register. \end{DoxyCompactList}\end{DoxyCompactItemize}


\doxysubsection{Member Data Documentation}
\mbox{\Hypertarget{structComSquare_1_1APU_1_1Registers_a0e72e8ea66b03c6a05b827a3b398f6fe}\label{structComSquare_1_1APU_1_1Registers_a0e72e8ea66b03c6a05b827a3b398f6fe}} 
\index{ComSquare::APU::Registers@{ComSquare::APU::Registers}!counter0@{counter0}}
\index{counter0@{counter0}!ComSquare::APU::Registers@{ComSquare::APU::Registers}}
\doxysubsubsection{\texorpdfstring{counter0}{counter0}}
{\footnotesize\ttfamily uint8\+\_\+t Com\+Square\+::\+A\+P\+U\+::\+Registers\+::counter0}



Counter-\/0 register. 

\mbox{\Hypertarget{structComSquare_1_1APU_1_1Registers_ac8a31fa1b2989fb34f5d167edf737b15}\label{structComSquare_1_1APU_1_1Registers_ac8a31fa1b2989fb34f5d167edf737b15}} 
\index{ComSquare::APU::Registers@{ComSquare::APU::Registers}!counter1@{counter1}}
\index{counter1@{counter1}!ComSquare::APU::Registers@{ComSquare::APU::Registers}}
\doxysubsubsection{\texorpdfstring{counter1}{counter1}}
{\footnotesize\ttfamily uint8\+\_\+t Com\+Square\+::\+A\+P\+U\+::\+Registers\+::counter1}



Counter-\/1 register. 

\mbox{\Hypertarget{structComSquare_1_1APU_1_1Registers_a888f86198d592c702cdc1c25fbe0e3f5}\label{structComSquare_1_1APU_1_1Registers_a888f86198d592c702cdc1c25fbe0e3f5}} 
\index{ComSquare::APU::Registers@{ComSquare::APU::Registers}!counter2@{counter2}}
\index{counter2@{counter2}!ComSquare::APU::Registers@{ComSquare::APU::Registers}}
\doxysubsubsection{\texorpdfstring{counter2}{counter2}}
{\footnotesize\ttfamily uint8\+\_\+t Com\+Square\+::\+A\+P\+U\+::\+Registers\+::counter2}



Counter-\/2 register. 

\mbox{\Hypertarget{structComSquare_1_1APU_1_1Registers_a1585ec8bcac768a022fedd51055bb880}\label{structComSquare_1_1APU_1_1Registers_a1585ec8bcac768a022fedd51055bb880}} 
\index{ComSquare::APU::Registers@{ComSquare::APU::Registers}!ctrlreg@{ctrlreg}}
\index{ctrlreg@{ctrlreg}!ComSquare::APU::Registers@{ComSquare::APU::Registers}}
\doxysubsubsection{\texorpdfstring{ctrlreg}{ctrlreg}}
{\footnotesize\ttfamily uint8\+\_\+t Com\+Square\+::\+A\+P\+U\+::\+Registers\+::ctrlreg}



Control Register register. 

\mbox{\Hypertarget{structComSquare_1_1APU_1_1Registers_ae047df53c9430cdf6f597fb9ff9c2cd9}\label{structComSquare_1_1APU_1_1Registers_ae047df53c9430cdf6f597fb9ff9c2cd9}} 
\index{ComSquare::APU::Registers@{ComSquare::APU::Registers}!dspregAddr@{dspregAddr}}
\index{dspregAddr@{dspregAddr}!ComSquare::APU::Registers@{ComSquare::APU::Registers}}
\doxysubsubsection{\texorpdfstring{dspregAddr}{dspregAddr}}
{\footnotesize\ttfamily uint8\+\_\+t Com\+Square\+::\+A\+P\+U\+::\+Registers\+::dspreg\+Addr}



\mbox{\hyperlink{namespaceComSquare_1_1APU_1_1DSP}{D\+SP}} Register Address register. 

\mbox{\Hypertarget{structComSquare_1_1APU_1_1Registers_abb9147763fef0f13c5e3773efd38fe0a}\label{structComSquare_1_1APU_1_1Registers_abb9147763fef0f13c5e3773efd38fe0a}} 
\index{ComSquare::APU::Registers@{ComSquare::APU::Registers}!dspregData@{dspregData}}
\index{dspregData@{dspregData}!ComSquare::APU::Registers@{ComSquare::APU::Registers}}
\doxysubsubsection{\texorpdfstring{dspregData}{dspregData}}
{\footnotesize\ttfamily uint8\+\_\+t Com\+Square\+::\+A\+P\+U\+::\+Registers\+::dspreg\+Data}



\mbox{\hyperlink{namespaceComSquare_1_1APU_1_1DSP}{D\+SP}} Register data register. 

\mbox{\Hypertarget{structComSquare_1_1APU_1_1Registers_a7596aa3a3d238924fb36b674a5b29723}\label{structComSquare_1_1APU_1_1Registers_a7596aa3a3d238924fb36b674a5b29723}} 
\index{ComSquare::APU::Registers@{ComSquare::APU::Registers}!port0@{port0}}
\index{port0@{port0}!ComSquare::APU::Registers@{ComSquare::APU::Registers}}
\doxysubsubsection{\texorpdfstring{port0}{port0}}
{\footnotesize\ttfamily uint8\+\_\+t Com\+Square\+::\+A\+P\+U\+::\+Registers\+::port0}



Port 0 register. 

\mbox{\Hypertarget{structComSquare_1_1APU_1_1Registers_aff7ac077d11b5cb170de27aa242d47d4}\label{structComSquare_1_1APU_1_1Registers_aff7ac077d11b5cb170de27aa242d47d4}} 
\index{ComSquare::APU::Registers@{ComSquare::APU::Registers}!port1@{port1}}
\index{port1@{port1}!ComSquare::APU::Registers@{ComSquare::APU::Registers}}
\doxysubsubsection{\texorpdfstring{port1}{port1}}
{\footnotesize\ttfamily uint8\+\_\+t Com\+Square\+::\+A\+P\+U\+::\+Registers\+::port1}



Port 1 register. 

\mbox{\Hypertarget{structComSquare_1_1APU_1_1Registers_a61577de367bc230163586c46d4959e9d}\label{structComSquare_1_1APU_1_1Registers_a61577de367bc230163586c46d4959e9d}} 
\index{ComSquare::APU::Registers@{ComSquare::APU::Registers}!port2@{port2}}
\index{port2@{port2}!ComSquare::APU::Registers@{ComSquare::APU::Registers}}
\doxysubsubsection{\texorpdfstring{port2}{port2}}
{\footnotesize\ttfamily uint8\+\_\+t Com\+Square\+::\+A\+P\+U\+::\+Registers\+::port2}



Port 2 register. 

\mbox{\Hypertarget{structComSquare_1_1APU_1_1Registers_a9661edea32acb0e434aa08cc4451a108}\label{structComSquare_1_1APU_1_1Registers_a9661edea32acb0e434aa08cc4451a108}} 
\index{ComSquare::APU::Registers@{ComSquare::APU::Registers}!port3@{port3}}
\index{port3@{port3}!ComSquare::APU::Registers@{ComSquare::APU::Registers}}
\doxysubsubsection{\texorpdfstring{port3}{port3}}
{\footnotesize\ttfamily uint8\+\_\+t Com\+Square\+::\+A\+P\+U\+::\+Registers\+::port3}



Port 3 register. 

\mbox{\Hypertarget{structComSquare_1_1APU_1_1Registers_a1b8880642a44bc70c8fa4703390c69e5}\label{structComSquare_1_1APU_1_1Registers_a1b8880642a44bc70c8fa4703390c69e5}} 
\index{ComSquare::APU::Registers@{ComSquare::APU::Registers}!regmem1@{regmem1}}
\index{regmem1@{regmem1}!ComSquare::APU::Registers@{ComSquare::APU::Registers}}
\doxysubsubsection{\texorpdfstring{regmem1}{regmem1}}
{\footnotesize\ttfamily uint8\+\_\+t Com\+Square\+::\+A\+P\+U\+::\+Registers\+::regmem1}



Regular \mbox{\hyperlink{namespaceComSquare_1_1Memory}{Memory}} register. 

\mbox{\Hypertarget{structComSquare_1_1APU_1_1Registers_a796c629e166e6a1dc1853b33556f83fa}\label{structComSquare_1_1APU_1_1Registers_a796c629e166e6a1dc1853b33556f83fa}} 
\index{ComSquare::APU::Registers@{ComSquare::APU::Registers}!regmem2@{regmem2}}
\index{regmem2@{regmem2}!ComSquare::APU::Registers@{ComSquare::APU::Registers}}
\doxysubsubsection{\texorpdfstring{regmem2}{regmem2}}
{\footnotesize\ttfamily uint8\+\_\+t Com\+Square\+::\+A\+P\+U\+::\+Registers\+::regmem2}



Another Regular \mbox{\hyperlink{namespaceComSquare_1_1Memory}{Memory}} register. 

\mbox{\Hypertarget{structComSquare_1_1APU_1_1Registers_ad0c1fb4090040f8bf28ecef922f88e92}\label{structComSquare_1_1APU_1_1Registers_ad0c1fb4090040f8bf28ecef922f88e92}} 
\index{ComSquare::APU::Registers@{ComSquare::APU::Registers}!timer0@{timer0}}
\index{timer0@{timer0}!ComSquare::APU::Registers@{ComSquare::APU::Registers}}
\doxysubsubsection{\texorpdfstring{timer0}{timer0}}
{\footnotesize\ttfamily uint8\+\_\+t Com\+Square\+::\+A\+P\+U\+::\+Registers\+::timer0}



Timer-\/0 register. 

\mbox{\Hypertarget{structComSquare_1_1APU_1_1Registers_a63d92eb8b1bcc693d7afcb587230f1d1}\label{structComSquare_1_1APU_1_1Registers_a63d92eb8b1bcc693d7afcb587230f1d1}} 
\index{ComSquare::APU::Registers@{ComSquare::APU::Registers}!timer1@{timer1}}
\index{timer1@{timer1}!ComSquare::APU::Registers@{ComSquare::APU::Registers}}
\doxysubsubsection{\texorpdfstring{timer1}{timer1}}
{\footnotesize\ttfamily uint8\+\_\+t Com\+Square\+::\+A\+P\+U\+::\+Registers\+::timer1}



Timer-\/1 register. 

\mbox{\Hypertarget{structComSquare_1_1APU_1_1Registers_a1707b3935184f283f0270526773d450b}\label{structComSquare_1_1APU_1_1Registers_a1707b3935184f283f0270526773d450b}} 
\index{ComSquare::APU::Registers@{ComSquare::APU::Registers}!timer2@{timer2}}
\index{timer2@{timer2}!ComSquare::APU::Registers@{ComSquare::APU::Registers}}
\doxysubsubsection{\texorpdfstring{timer2}{timer2}}
{\footnotesize\ttfamily uint8\+\_\+t Com\+Square\+::\+A\+P\+U\+::\+Registers\+::timer2}



Timer-\/2 register. 

\mbox{\Hypertarget{structComSquare_1_1APU_1_1Registers_abdfe3b23ea43931f53f9f66b83ea9129}\label{structComSquare_1_1APU_1_1Registers_abdfe3b23ea43931f53f9f66b83ea9129}} 
\index{ComSquare::APU::Registers@{ComSquare::APU::Registers}!unknown@{unknown}}
\index{unknown@{unknown}!ComSquare::APU::Registers@{ComSquare::APU::Registers}}
\doxysubsubsection{\texorpdfstring{unknown}{unknown}}
{\footnotesize\ttfamily uint8\+\_\+t Com\+Square\+::\+A\+P\+U\+::\+Registers\+::unknown}



An undocumented register. 



The documentation for this struct was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
sources/\+A\+P\+U/\mbox{\hyperlink{APU_8hpp}{A\+P\+U.\+hpp}}\end{DoxyCompactItemize}
