\hypertarget{classComSquare_1_1Memory_1_1MemoryBus}{}\doxysection{Com\+Square\+::Memory\+::Memory\+Bus Class Reference}
\label{classComSquare_1_1Memory_1_1MemoryBus}\index{ComSquare::Memory::MemoryBus@{ComSquare::Memory::MemoryBus}}


The memory bus is the component responsible of mapping addresses to components address and transmitting the data.  




{\ttfamily \#include $<$Memory\+Bus.\+hpp$>$}



Collaboration diagram for Com\+Square\+::Memory\+::Memory\+Bus\+:\nopagebreak
\begin{figure}[H]
\begin{center}
\leavevmode
\includegraphics[width=208pt]{classComSquare_1_1Memory_1_1MemoryBus__coll__graph}
\end{center}
\end{figure}
\doxysubsection*{Public Member Functions}
\begin{DoxyCompactItemize}
\item 
uint8\+\_\+t \mbox{\hyperlink{classComSquare_1_1Memory_1_1MemoryBus_a66fe80e0dafb6078eabf809b2ecd6dae}{read}} (\mbox{\hyperlink{Ints_8hpp_a89f009aaf5d1964a000f44f09fa0bcf8}{uint24\+\_\+t}} addr)
\begin{DoxyCompactList}\small\item\em Read data at a global address. \end{DoxyCompactList}\item 
void \mbox{\hyperlink{classComSquare_1_1Memory_1_1MemoryBus_a1387b77513d9e0d077291477faab46cd}{write}} (\mbox{\hyperlink{Ints_8hpp_a89f009aaf5d1964a000f44f09fa0bcf8}{uint24\+\_\+t}} addr, uint8\+\_\+t data)
\begin{DoxyCompactList}\small\item\em Write a data to a global address. \end{DoxyCompactList}\item 
void \mbox{\hyperlink{classComSquare_1_1Memory_1_1MemoryBus_a21e37ae17ad577a34af5ba49fbdf7180}{map\+Components}} (\mbox{\hyperlink{structComSquare_1_1SNES}{S\+N\+ES}} \&console)
\begin{DoxyCompactList}\small\item\em Map components to the address space using the currently loaded cartridge to set the right mapping mode. \end{DoxyCompactList}\end{DoxyCompactItemize}
\doxysubsection*{Private Member Functions}
\begin{DoxyCompactItemize}
\item 
std\+::shared\+\_\+ptr$<$ \mbox{\hyperlink{classComSquare_1_1Memory_1_1IMemory}{I\+Memory}} $>$ \mbox{\hyperlink{classComSquare_1_1Memory_1_1MemoryBus_a1b7ba0ca63589d971404e1b7031f26c1}{get\+Accessor}} (\mbox{\hyperlink{Ints_8hpp_a89f009aaf5d1964a000f44f09fa0bcf8}{uint24\+\_\+t}} addr)
\begin{DoxyCompactList}\small\item\em Helper function to get the components that is responsible of read/write at an address. \end{DoxyCompactList}\item 
void \mbox{\hyperlink{classComSquare_1_1Memory_1_1MemoryBus_afa5f49e6918eb466bc9116f042c7c636}{\+\_\+mirror\+Components}} (\mbox{\hyperlink{structComSquare_1_1SNES}{S\+N\+ES}} \&console, \mbox{\hyperlink{CMakeCache_8txt_a79a3d8790b2588b09777910863574e09}{int}} i)
\begin{DoxyCompactList}\small\item\em W\+Ram, \mbox{\hyperlink{namespaceComSquare_1_1CPU}{C\+PU}}, \mbox{\hyperlink{namespaceComSquare_1_1PPU}{P\+PU}} \& A\+LU registers are mirrored to all banks of Q1 \& Q3. This function is used for the mirroring. \end{DoxyCompactList}\end{DoxyCompactItemize}
\doxysubsection*{Private Attributes}
\begin{DoxyCompactItemize}
\item 
std\+::vector$<$ std\+::shared\+\_\+ptr$<$ \mbox{\hyperlink{classComSquare_1_1Memory_1_1IMemory}{I\+Memory}} $>$ $>$ \mbox{\hyperlink{classComSquare_1_1Memory_1_1MemoryBus_a2c2385dddba2ec8f143f2d88a58a9431}{\+\_\+memory\+Accessors}}
\begin{DoxyCompactList}\small\item\em The list of components registered inside the bus. Every components that can read/write to a public address should be in this vector. \end{DoxyCompactList}\item 
uint8\+\_\+t \mbox{\hyperlink{classComSquare_1_1Memory_1_1MemoryBus_ab55064b581ef9348bc47e0f277a0439d}{\+\_\+openbus}} = 0
\begin{DoxyCompactList}\small\item\em The last value read via the memory bus. \end{DoxyCompactList}\end{DoxyCompactItemize}


\doxysubsection{Detailed Description}
The memory bus is the component responsible of mapping addresses to components address and transmitting the data. 

\doxysubsection{Member Function Documentation}
\mbox{\Hypertarget{classComSquare_1_1Memory_1_1MemoryBus_afa5f49e6918eb466bc9116f042c7c636}\label{classComSquare_1_1Memory_1_1MemoryBus_afa5f49e6918eb466bc9116f042c7c636}} 
\index{ComSquare::Memory::MemoryBus@{ComSquare::Memory::MemoryBus}!\_mirrorComponents@{\_mirrorComponents}}
\index{\_mirrorComponents@{\_mirrorComponents}!ComSquare::Memory::MemoryBus@{ComSquare::Memory::MemoryBus}}
\doxysubsubsection{\texorpdfstring{\_mirrorComponents()}{\_mirrorComponents()}}
{\footnotesize\ttfamily void Com\+Square\+::\+Memory\+::\+Memory\+Bus\+::\+\_\+mirror\+Components (\begin{DoxyParamCaption}\item[{\mbox{\hyperlink{structComSquare_1_1SNES}{S\+N\+ES}} \&}]{console,  }\item[{\mbox{\hyperlink{CMakeCache_8txt_a79a3d8790b2588b09777910863574e09}{int}}}]{i }\end{DoxyParamCaption})\hspace{0.3cm}{\ttfamily [inline]}, {\ttfamily [private]}}



W\+Ram, \mbox{\hyperlink{namespaceComSquare_1_1CPU}{C\+PU}}, \mbox{\hyperlink{namespaceComSquare_1_1PPU}{P\+PU}} \& A\+LU registers are mirrored to all banks of Q1 \& Q3. This function is used for the mirroring. 


\begin{DoxyParams}{Parameters}
{\em console} & All the components. \\
\hline
{\em i} & Base address for the mirrors. \\
\hline
\end{DoxyParams}
\mbox{\Hypertarget{classComSquare_1_1Memory_1_1MemoryBus_a1b7ba0ca63589d971404e1b7031f26c1}\label{classComSquare_1_1Memory_1_1MemoryBus_a1b7ba0ca63589d971404e1b7031f26c1}} 
\index{ComSquare::Memory::MemoryBus@{ComSquare::Memory::MemoryBus}!getAccessor@{getAccessor}}
\index{getAccessor@{getAccessor}!ComSquare::Memory::MemoryBus@{ComSquare::Memory::MemoryBus}}
\doxysubsubsection{\texorpdfstring{getAccessor()}{getAccessor()}}
{\footnotesize\ttfamily std\+::shared\+\_\+ptr$<$ \mbox{\hyperlink{classComSquare_1_1Memory_1_1IMemory}{I\+Memory}} $>$ Com\+Square\+::\+Memory\+::\+Memory\+Bus\+::get\+Accessor (\begin{DoxyParamCaption}\item[{\mbox{\hyperlink{Ints_8hpp_a89f009aaf5d1964a000f44f09fa0bcf8}{uint24\+\_\+t}}}]{addr }\end{DoxyParamCaption})\hspace{0.3cm}{\ttfamily [private]}}



Helper function to get the components that is responsible of read/write at an address. 


\begin{DoxyParams}{Parameters}
{\em addr} & The address you want to look for. \\
\hline
\end{DoxyParams}
\begin{DoxyReturn}{Returns}
The components responsible for the address param or nullptr if none was found. 
\end{DoxyReturn}
\mbox{\Hypertarget{classComSquare_1_1Memory_1_1MemoryBus_a21e37ae17ad577a34af5ba49fbdf7180}\label{classComSquare_1_1Memory_1_1MemoryBus_a21e37ae17ad577a34af5ba49fbdf7180}} 
\index{ComSquare::Memory::MemoryBus@{ComSquare::Memory::MemoryBus}!mapComponents@{mapComponents}}
\index{mapComponents@{mapComponents}!ComSquare::Memory::MemoryBus@{ComSquare::Memory::MemoryBus}}
\doxysubsubsection{\texorpdfstring{mapComponents()}{mapComponents()}}
{\footnotesize\ttfamily void Com\+Square\+::\+Memory\+::\+Memory\+Bus\+::map\+Components (\begin{DoxyParamCaption}\item[{\mbox{\hyperlink{structComSquare_1_1SNES}{S\+N\+ES}} \&}]{console }\end{DoxyParamCaption})}



Map components to the address space using the currently loaded cartridge to set the right mapping mode. 


\begin{DoxyParams}{Parameters}
{\em console} & All the components. \\
\hline
\end{DoxyParams}
\mbox{\Hypertarget{classComSquare_1_1Memory_1_1MemoryBus_a66fe80e0dafb6078eabf809b2ecd6dae}\label{classComSquare_1_1Memory_1_1MemoryBus_a66fe80e0dafb6078eabf809b2ecd6dae}} 
\index{ComSquare::Memory::MemoryBus@{ComSquare::Memory::MemoryBus}!read@{read}}
\index{read@{read}!ComSquare::Memory::MemoryBus@{ComSquare::Memory::MemoryBus}}
\doxysubsubsection{\texorpdfstring{read()}{read()}}
{\footnotesize\ttfamily uint8\+\_\+t Com\+Square\+::\+Memory\+::\+Memory\+Bus\+::read (\begin{DoxyParamCaption}\item[{\mbox{\hyperlink{Ints_8hpp_a89f009aaf5d1964a000f44f09fa0bcf8}{uint24\+\_\+t}}}]{addr }\end{DoxyParamCaption})}



Read data at a global address. 


\begin{DoxyParams}{Parameters}
{\em addr} & The address to read from. \\
\hline
\end{DoxyParams}
\begin{DoxyReturn}{Returns}
The value that the component returned for this address. If the address was mapped to ram, it simply returned the value. If the address was mapped to a register the component returned the register. 
\end{DoxyReturn}
\mbox{\Hypertarget{classComSquare_1_1Memory_1_1MemoryBus_a1387b77513d9e0d077291477faab46cd}\label{classComSquare_1_1Memory_1_1MemoryBus_a1387b77513d9e0d077291477faab46cd}} 
\index{ComSquare::Memory::MemoryBus@{ComSquare::Memory::MemoryBus}!write@{write}}
\index{write@{write}!ComSquare::Memory::MemoryBus@{ComSquare::Memory::MemoryBus}}
\doxysubsubsection{\texorpdfstring{write()}{write()}}
{\footnotesize\ttfamily void Com\+Square\+::\+Memory\+::\+Memory\+Bus\+::write (\begin{DoxyParamCaption}\item[{\mbox{\hyperlink{Ints_8hpp_a89f009aaf5d1964a000f44f09fa0bcf8}{uint24\+\_\+t}}}]{addr,  }\item[{uint8\+\_\+t}]{data }\end{DoxyParamCaption})}



Write a data to a global address. 


\begin{DoxyParams}{Parameters}
{\em addr} & The address to write to. \\
\hline
{\em data} & The data to write. \\
\hline
\end{DoxyParams}


\doxysubsection{Member Data Documentation}
\mbox{\Hypertarget{classComSquare_1_1Memory_1_1MemoryBus_a2c2385dddba2ec8f143f2d88a58a9431}\label{classComSquare_1_1Memory_1_1MemoryBus_a2c2385dddba2ec8f143f2d88a58a9431}} 
\index{ComSquare::Memory::MemoryBus@{ComSquare::Memory::MemoryBus}!\_memoryAccessors@{\_memoryAccessors}}
\index{\_memoryAccessors@{\_memoryAccessors}!ComSquare::Memory::MemoryBus@{ComSquare::Memory::MemoryBus}}
\doxysubsubsection{\texorpdfstring{\_memoryAccessors}{\_memoryAccessors}}
{\footnotesize\ttfamily std\+::vector$<$std\+::shared\+\_\+ptr$<$\mbox{\hyperlink{classComSquare_1_1Memory_1_1IMemory}{I\+Memory}}$>$ $>$ Com\+Square\+::\+Memory\+::\+Memory\+Bus\+::\+\_\+memory\+Accessors\hspace{0.3cm}{\ttfamily [private]}}



The list of components registered inside the bus. Every components that can read/write to a public address should be in this vector. 

\mbox{\Hypertarget{classComSquare_1_1Memory_1_1MemoryBus_ab55064b581ef9348bc47e0f277a0439d}\label{classComSquare_1_1Memory_1_1MemoryBus_ab55064b581ef9348bc47e0f277a0439d}} 
\index{ComSquare::Memory::MemoryBus@{ComSquare::Memory::MemoryBus}!\_openBus@{\_openBus}}
\index{\_openBus@{\_openBus}!ComSquare::Memory::MemoryBus@{ComSquare::Memory::MemoryBus}}
\doxysubsubsection{\texorpdfstring{\_openBus}{\_openBus}}
{\footnotesize\ttfamily uint8\+\_\+t Com\+Square\+::\+Memory\+::\+Memory\+Bus\+::\+\_\+openbus = 0\hspace{0.3cm}{\ttfamily [private]}}



The last value read via the memory bus. 



The documentation for this class was generated from the following files\+:\begin{DoxyCompactItemize}
\item 
sources/\+Memory/\mbox{\hyperlink{MemoryBus_8hpp}{Memory\+Bus.\+hpp}}\item 
sources/\+Memory/\mbox{\hyperlink{MemoryBus_8cpp}{Memory\+Bus.\+cpp}}\end{DoxyCompactItemize}
