\hypertarget{structComSquare_1_1CPU_1_1InternalRegisters}{}\doxysection{Com\+Square\+::C\+PU\+::Internal\+Registers Struct Reference}
\label{structComSquare_1_1CPU_1_1InternalRegisters}\index{ComSquare::CPU::InternalRegisters@{ComSquare::CPU::InternalRegisters}}


Struct containing internal registers of the \mbox{\hyperlink{classComSquare_1_1CPU_1_1CPU}{C\+PU}}.  




{\ttfamily \#include $<$C\+P\+U.\+hpp$>$}



Collaboration diagram for Com\+Square\+::C\+PU\+::Internal\+Registers\+:\nopagebreak
\begin{figure}[H]
\begin{center}
\leavevmode
\includegraphics[width=223pt]{structComSquare_1_1CPU_1_1InternalRegisters__coll__graph}
\end{center}
\end{figure}
\doxysubsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
uint8\+\_\+t \mbox{\hyperlink{structComSquare_1_1CPU_1_1InternalRegisters_a45c471c6c5cef4d6a117e223b8a19ed1}{nmitimen}}
\begin{DoxyCompactList}\small\item\em Interrupt Enable Register. \end{DoxyCompactList}\item 
uint8\+\_\+t \mbox{\hyperlink{structComSquare_1_1CPU_1_1InternalRegisters_afac8a1b505dff6a6aa9416392e469471}{wrio}}
\begin{DoxyCompactList}\small\item\em IO Port Write Register. \end{DoxyCompactList}\item 
uint8\+\_\+t \mbox{\hyperlink{structComSquare_1_1CPU_1_1InternalRegisters_a0ec804218ae29f8ad4b8019dd78dc38f}{wrmpya}}
\begin{DoxyCompactList}\small\item\em Multiplicand Register A. \end{DoxyCompactList}\item 
uint8\+\_\+t \mbox{\hyperlink{structComSquare_1_1CPU_1_1InternalRegisters_a258f0d486b05d1d77f39b3c10f6eaaf5}{wrmpyb}}
\begin{DoxyCompactList}\small\item\em Multiplicand Register B. \end{DoxyCompactList}\item 
uint8\+\_\+t \mbox{\hyperlink{structComSquare_1_1CPU_1_1InternalRegisters_ae98022af2fc7c80062444e9cecf95f0e}{wrdivl}}
\begin{DoxyCompactList}\small\item\em Divisor \& Dividend \mbox{\hyperlink{structComSquare_1_1CPU_1_1Registers}{Registers}} (A -\/ Low) \end{DoxyCompactList}\item 
uint8\+\_\+t \mbox{\hyperlink{structComSquare_1_1CPU_1_1InternalRegisters_aa315eec822cf92ec586c2ba918a36e00}{wrdivh}}
\begin{DoxyCompactList}\small\item\em Divisor \& Dividend \mbox{\hyperlink{structComSquare_1_1CPU_1_1Registers}{Registers}} (A -\/ High) \end{DoxyCompactList}\item 
uint8\+\_\+t \mbox{\hyperlink{structComSquare_1_1CPU_1_1InternalRegisters_aa1466fa14182549898886e3eb3074f36}{wrdivb}}
\begin{DoxyCompactList}\small\item\em Divisor \& Dividend \mbox{\hyperlink{structComSquare_1_1CPU_1_1Registers}{Registers}} (B) \end{DoxyCompactList}\item 
uint8\+\_\+t \mbox{\hyperlink{structComSquare_1_1CPU_1_1InternalRegisters_a030f0f2142ee49187735f82876bd12e8}{htimel}}
\begin{DoxyCompactList}\small\item\em I\+RQ Timer \mbox{\hyperlink{structComSquare_1_1CPU_1_1Registers}{Registers}} (Horizontal -\/ Low) \end{DoxyCompactList}\item 
uint8\+\_\+t \mbox{\hyperlink{structComSquare_1_1CPU_1_1InternalRegisters_a538141acc2e0eeac8f1e801940929539}{htimeh}}
\begin{DoxyCompactList}\small\item\em I\+RQ Timer \mbox{\hyperlink{structComSquare_1_1CPU_1_1Registers}{Registers}} (Horizontal -\/ High) \end{DoxyCompactList}\item 
uint8\+\_\+t \mbox{\hyperlink{structComSquare_1_1CPU_1_1InternalRegisters_a6262d0ba292853c4232d24b6142e1acf}{vtimel}}
\begin{DoxyCompactList}\small\item\em I\+RQ Timer \mbox{\hyperlink{structComSquare_1_1CPU_1_1Registers}{Registers}} (Vertical -\/ Low) \end{DoxyCompactList}\item 
uint8\+\_\+t \mbox{\hyperlink{structComSquare_1_1CPU_1_1InternalRegisters_a24e773242680bd43e8d6a0fcd2e1ea48}{vtimeh}}
\begin{DoxyCompactList}\small\item\em I\+RQ Timer \mbox{\hyperlink{structComSquare_1_1CPU_1_1Registers}{Registers}} (Vertical -\/ High) \end{DoxyCompactList}\item 
uint8\+\_\+t \mbox{\hyperlink{structComSquare_1_1CPU_1_1InternalRegisters_ab51577c6d3509770c1144e45932ee38c}{mdmaen}}
\begin{DoxyCompactList}\small\item\em D\+MA Enable Register. \end{DoxyCompactList}\item 
uint8\+\_\+t \mbox{\hyperlink{structComSquare_1_1CPU_1_1InternalRegisters_af2f3e7f51a783a517b71639de897fc3c}{hdmaen}}
\begin{DoxyCompactList}\small\item\em H\+D\+MA Enable Register. \end{DoxyCompactList}\item 
uint8\+\_\+t \mbox{\hyperlink{structComSquare_1_1CPU_1_1InternalRegisters_aa3dda181d78b6bcd50057d83c97ecb2c}{memsel}}
\begin{DoxyCompactList}\small\item\em R\+OM Speed Register. \end{DoxyCompactList}\item 
uint8\+\_\+t \mbox{\hyperlink{structComSquare_1_1CPU_1_1InternalRegisters_ac49c0aaf5eb44afe572930b1bfe13c00}{rdnmi}}
\begin{DoxyCompactList}\small\item\em Interrupt Flag \mbox{\hyperlink{structComSquare_1_1CPU_1_1Registers}{Registers}}. \end{DoxyCompactList}\item 
uint8\+\_\+t \mbox{\hyperlink{structComSquare_1_1CPU_1_1InternalRegisters_a0058417dd2f115ffd67c909b227552f8}{timeup}}
\begin{DoxyCompactList}\small\item\em Interrupt Flag \mbox{\hyperlink{structComSquare_1_1CPU_1_1Registers}{Registers}} -\/ Time\+Up. \end{DoxyCompactList}\item 
uint8\+\_\+t \mbox{\hyperlink{structComSquare_1_1CPU_1_1InternalRegisters_ac04e82f935ec316b6d2433dea7df36f0}{hvbjoy}}
\begin{DoxyCompactList}\small\item\em \mbox{\hyperlink{namespaceComSquare_1_1PPU}{P\+PU}} Status Register. \end{DoxyCompactList}\item 
uint8\+\_\+t \mbox{\hyperlink{structComSquare_1_1CPU_1_1InternalRegisters_acd1644bf64088f00ebeb2d62fe90fbe2}{rdio}}
\begin{DoxyCompactList}\small\item\em IO Port Read Register. \end{DoxyCompactList}\item 
uint8\+\_\+t \mbox{\hyperlink{structComSquare_1_1CPU_1_1InternalRegisters_a18401a7dbfe4784b6367623cac251a5e}{rddivl}}
\begin{DoxyCompactList}\small\item\em Divide Result \mbox{\hyperlink{structComSquare_1_1CPU_1_1Registers}{Registers}} (can sometimes be used as multiplication result register) -\/ L\+OW. \end{DoxyCompactList}\item 
uint8\+\_\+t \mbox{\hyperlink{structComSquare_1_1CPU_1_1InternalRegisters_a70602e356a792a14a1b638d692556e8c}{rddivh}}
\begin{DoxyCompactList}\small\item\em Divide Result \mbox{\hyperlink{structComSquare_1_1CPU_1_1Registers}{Registers}} (can sometimes be used as multiplication result register) -\/ H\+I\+GH. \end{DoxyCompactList}\item 
uint8\+\_\+t \mbox{\hyperlink{structComSquare_1_1CPU_1_1InternalRegisters_a87261625195bb3f38db9354a29334ddf}{rdmpyl}}
\begin{DoxyCompactList}\small\item\em Multiplication Result \mbox{\hyperlink{structComSquare_1_1CPU_1_1Registers}{Registers}} (can sometimes be used as divide result register) -\/ L\+OW. \end{DoxyCompactList}\item 
uint8\+\_\+t \mbox{\hyperlink{structComSquare_1_1CPU_1_1InternalRegisters_a79c946893be3148b0c72d9da2c8f3428}{rdmpyh}}
\begin{DoxyCompactList}\small\item\em Multiplication Result \mbox{\hyperlink{structComSquare_1_1CPU_1_1Registers}{Registers}} (can sometimes be used as divide result register) -\/ H\+I\+GH. \end{DoxyCompactList}\item 
uint8\+\_\+t \mbox{\hyperlink{structComSquare_1_1CPU_1_1InternalRegisters_ab17acbbf524b6bfb9a8006ce87e9148b}{joy1l}}
\begin{DoxyCompactList}\small\item\em Controller Port Data \mbox{\hyperlink{structComSquare_1_1CPU_1_1Registers}{Registers}} (Pad 1 -\/ Low) \end{DoxyCompactList}\item 
uint8\+\_\+t \mbox{\hyperlink{structComSquare_1_1CPU_1_1InternalRegisters_a5a252a845daf5137bb251933a5812265}{joy1h}}
\begin{DoxyCompactList}\small\item\em Controller Port Data \mbox{\hyperlink{structComSquare_1_1CPU_1_1Registers}{Registers}} (Pad 1 -\/ High) \end{DoxyCompactList}\item 
uint8\+\_\+t \mbox{\hyperlink{structComSquare_1_1CPU_1_1InternalRegisters_a85d9e842e61f9c4ef519b42b4b8748be}{joy2l}}
\begin{DoxyCompactList}\small\item\em Controller Port Data \mbox{\hyperlink{structComSquare_1_1CPU_1_1Registers}{Registers}} (Pad 2 -\/ Low) \end{DoxyCompactList}\item 
uint8\+\_\+t \mbox{\hyperlink{structComSquare_1_1CPU_1_1InternalRegisters_af37f63c18abd719f6a7f6b2cd009b9e5}{joy2h}}
\begin{DoxyCompactList}\small\item\em Controller Port Data \mbox{\hyperlink{structComSquare_1_1CPU_1_1Registers}{Registers}} (Pad 2 -\/ High) \end{DoxyCompactList}\item 
uint8\+\_\+t \mbox{\hyperlink{structComSquare_1_1CPU_1_1InternalRegisters_ad64b7d047996ea04e65e4e84f341af37}{joy3l}}
\begin{DoxyCompactList}\small\item\em Controller Port Data \mbox{\hyperlink{structComSquare_1_1CPU_1_1Registers}{Registers}} (Pad 3 -\/ Low) \end{DoxyCompactList}\item 
uint8\+\_\+t \mbox{\hyperlink{structComSquare_1_1CPU_1_1InternalRegisters_aaa5a1939600968d066561ea8056cfca9}{joy3h}}
\begin{DoxyCompactList}\small\item\em Controller Port Data \mbox{\hyperlink{structComSquare_1_1CPU_1_1Registers}{Registers}} (Pad 3 -\/ High) \end{DoxyCompactList}\item 
uint8\+\_\+t \mbox{\hyperlink{structComSquare_1_1CPU_1_1InternalRegisters_a85afe00843e4f9616fa106c3ae610919}{joy4l}}
\begin{DoxyCompactList}\small\item\em Controller Port Data \mbox{\hyperlink{structComSquare_1_1CPU_1_1Registers}{Registers}} (Pad 4 -\/ Low) \end{DoxyCompactList}\item 
uint8\+\_\+t \mbox{\hyperlink{structComSquare_1_1CPU_1_1InternalRegisters_a6bb83a780752963fefbe50be5d3a026d}{joy4h}}
\begin{DoxyCompactList}\small\item\em Controller Port Data \mbox{\hyperlink{structComSquare_1_1CPU_1_1Registers}{Registers}} (Pad 4 -\/ High) \end{DoxyCompactList}\end{DoxyCompactItemize}


\doxysubsection{Detailed Description}
Struct containing internal registers of the \mbox{\hyperlink{classComSquare_1_1CPU_1_1CPU}{C\+PU}}. 

\doxysubsection{Member Data Documentation}
\mbox{\Hypertarget{structComSquare_1_1CPU_1_1InternalRegisters_af2f3e7f51a783a517b71639de897fc3c}\label{structComSquare_1_1CPU_1_1InternalRegisters_af2f3e7f51a783a517b71639de897fc3c}} 
\index{ComSquare::CPU::InternalRegisters@{ComSquare::CPU::InternalRegisters}!hdmaen@{hdmaen}}
\index{hdmaen@{hdmaen}!ComSquare::CPU::InternalRegisters@{ComSquare::CPU::InternalRegisters}}
\doxysubsubsection{\texorpdfstring{hdmaen}{hdmaen}}
{\footnotesize\ttfamily uint8\+\_\+t Com\+Square\+::\+C\+P\+U\+::\+Internal\+Registers\+::hdmaen}



H\+D\+MA Enable Register. 

\mbox{\Hypertarget{structComSquare_1_1CPU_1_1InternalRegisters_a538141acc2e0eeac8f1e801940929539}\label{structComSquare_1_1CPU_1_1InternalRegisters_a538141acc2e0eeac8f1e801940929539}} 
\index{ComSquare::CPU::InternalRegisters@{ComSquare::CPU::InternalRegisters}!htimeh@{htimeh}}
\index{htimeh@{htimeh}!ComSquare::CPU::InternalRegisters@{ComSquare::CPU::InternalRegisters}}
\doxysubsubsection{\texorpdfstring{htimeh}{htimeh}}
{\footnotesize\ttfamily uint8\+\_\+t Com\+Square\+::\+C\+P\+U\+::\+Internal\+Registers\+::htimeh}



I\+RQ Timer \mbox{\hyperlink{structComSquare_1_1CPU_1_1Registers}{Registers}} (Horizontal -\/ High) 

\mbox{\Hypertarget{structComSquare_1_1CPU_1_1InternalRegisters_a030f0f2142ee49187735f82876bd12e8}\label{structComSquare_1_1CPU_1_1InternalRegisters_a030f0f2142ee49187735f82876bd12e8}} 
\index{ComSquare::CPU::InternalRegisters@{ComSquare::CPU::InternalRegisters}!htimel@{htimel}}
\index{htimel@{htimel}!ComSquare::CPU::InternalRegisters@{ComSquare::CPU::InternalRegisters}}
\doxysubsubsection{\texorpdfstring{htimel}{htimel}}
{\footnotesize\ttfamily uint8\+\_\+t Com\+Square\+::\+C\+P\+U\+::\+Internal\+Registers\+::htimel}



I\+RQ Timer \mbox{\hyperlink{structComSquare_1_1CPU_1_1Registers}{Registers}} (Horizontal -\/ Low) 

\mbox{\Hypertarget{structComSquare_1_1CPU_1_1InternalRegisters_ac04e82f935ec316b6d2433dea7df36f0}\label{structComSquare_1_1CPU_1_1InternalRegisters_ac04e82f935ec316b6d2433dea7df36f0}} 
\index{ComSquare::CPU::InternalRegisters@{ComSquare::CPU::InternalRegisters}!hvbjoy@{hvbjoy}}
\index{hvbjoy@{hvbjoy}!ComSquare::CPU::InternalRegisters@{ComSquare::CPU::InternalRegisters}}
\doxysubsubsection{\texorpdfstring{hvbjoy}{hvbjoy}}
{\footnotesize\ttfamily uint8\+\_\+t Com\+Square\+::\+C\+P\+U\+::\+Internal\+Registers\+::hvbjoy}



\mbox{\hyperlink{namespaceComSquare_1_1PPU}{P\+PU}} Status Register. 

\mbox{\Hypertarget{structComSquare_1_1CPU_1_1InternalRegisters_a5a252a845daf5137bb251933a5812265}\label{structComSquare_1_1CPU_1_1InternalRegisters_a5a252a845daf5137bb251933a5812265}} 
\index{ComSquare::CPU::InternalRegisters@{ComSquare::CPU::InternalRegisters}!joy1h@{joy1h}}
\index{joy1h@{joy1h}!ComSquare::CPU::InternalRegisters@{ComSquare::CPU::InternalRegisters}}
\doxysubsubsection{\texorpdfstring{joy1h}{joy1h}}
{\footnotesize\ttfamily uint8\+\_\+t Com\+Square\+::\+C\+P\+U\+::\+Internal\+Registers\+::joy1h}



Controller Port Data \mbox{\hyperlink{structComSquare_1_1CPU_1_1Registers}{Registers}} (Pad 1 -\/ High) 

\mbox{\Hypertarget{structComSquare_1_1CPU_1_1InternalRegisters_ab17acbbf524b6bfb9a8006ce87e9148b}\label{structComSquare_1_1CPU_1_1InternalRegisters_ab17acbbf524b6bfb9a8006ce87e9148b}} 
\index{ComSquare::CPU::InternalRegisters@{ComSquare::CPU::InternalRegisters}!joy1l@{joy1l}}
\index{joy1l@{joy1l}!ComSquare::CPU::InternalRegisters@{ComSquare::CPU::InternalRegisters}}
\doxysubsubsection{\texorpdfstring{joy1l}{joy1l}}
{\footnotesize\ttfamily uint8\+\_\+t Com\+Square\+::\+C\+P\+U\+::\+Internal\+Registers\+::joy1l}



Controller Port Data \mbox{\hyperlink{structComSquare_1_1CPU_1_1Registers}{Registers}} (Pad 1 -\/ Low) 

\mbox{\Hypertarget{structComSquare_1_1CPU_1_1InternalRegisters_af37f63c18abd719f6a7f6b2cd009b9e5}\label{structComSquare_1_1CPU_1_1InternalRegisters_af37f63c18abd719f6a7f6b2cd009b9e5}} 
\index{ComSquare::CPU::InternalRegisters@{ComSquare::CPU::InternalRegisters}!joy2h@{joy2h}}
\index{joy2h@{joy2h}!ComSquare::CPU::InternalRegisters@{ComSquare::CPU::InternalRegisters}}
\doxysubsubsection{\texorpdfstring{joy2h}{joy2h}}
{\footnotesize\ttfamily uint8\+\_\+t Com\+Square\+::\+C\+P\+U\+::\+Internal\+Registers\+::joy2h}



Controller Port Data \mbox{\hyperlink{structComSquare_1_1CPU_1_1Registers}{Registers}} (Pad 2 -\/ High) 

\mbox{\Hypertarget{structComSquare_1_1CPU_1_1InternalRegisters_a85d9e842e61f9c4ef519b42b4b8748be}\label{structComSquare_1_1CPU_1_1InternalRegisters_a85d9e842e61f9c4ef519b42b4b8748be}} 
\index{ComSquare::CPU::InternalRegisters@{ComSquare::CPU::InternalRegisters}!joy2l@{joy2l}}
\index{joy2l@{joy2l}!ComSquare::CPU::InternalRegisters@{ComSquare::CPU::InternalRegisters}}
\doxysubsubsection{\texorpdfstring{joy2l}{joy2l}}
{\footnotesize\ttfamily uint8\+\_\+t Com\+Square\+::\+C\+P\+U\+::\+Internal\+Registers\+::joy2l}



Controller Port Data \mbox{\hyperlink{structComSquare_1_1CPU_1_1Registers}{Registers}} (Pad 2 -\/ Low) 

\mbox{\Hypertarget{structComSquare_1_1CPU_1_1InternalRegisters_aaa5a1939600968d066561ea8056cfca9}\label{structComSquare_1_1CPU_1_1InternalRegisters_aaa5a1939600968d066561ea8056cfca9}} 
\index{ComSquare::CPU::InternalRegisters@{ComSquare::CPU::InternalRegisters}!joy3h@{joy3h}}
\index{joy3h@{joy3h}!ComSquare::CPU::InternalRegisters@{ComSquare::CPU::InternalRegisters}}
\doxysubsubsection{\texorpdfstring{joy3h}{joy3h}}
{\footnotesize\ttfamily uint8\+\_\+t Com\+Square\+::\+C\+P\+U\+::\+Internal\+Registers\+::joy3h}



Controller Port Data \mbox{\hyperlink{structComSquare_1_1CPU_1_1Registers}{Registers}} (Pad 3 -\/ High) 

\mbox{\Hypertarget{structComSquare_1_1CPU_1_1InternalRegisters_ad64b7d047996ea04e65e4e84f341af37}\label{structComSquare_1_1CPU_1_1InternalRegisters_ad64b7d047996ea04e65e4e84f341af37}} 
\index{ComSquare::CPU::InternalRegisters@{ComSquare::CPU::InternalRegisters}!joy3l@{joy3l}}
\index{joy3l@{joy3l}!ComSquare::CPU::InternalRegisters@{ComSquare::CPU::InternalRegisters}}
\doxysubsubsection{\texorpdfstring{joy3l}{joy3l}}
{\footnotesize\ttfamily uint8\+\_\+t Com\+Square\+::\+C\+P\+U\+::\+Internal\+Registers\+::joy3l}



Controller Port Data \mbox{\hyperlink{structComSquare_1_1CPU_1_1Registers}{Registers}} (Pad 3 -\/ Low) 

\mbox{\Hypertarget{structComSquare_1_1CPU_1_1InternalRegisters_a6bb83a780752963fefbe50be5d3a026d}\label{structComSquare_1_1CPU_1_1InternalRegisters_a6bb83a780752963fefbe50be5d3a026d}} 
\index{ComSquare::CPU::InternalRegisters@{ComSquare::CPU::InternalRegisters}!joy4h@{joy4h}}
\index{joy4h@{joy4h}!ComSquare::CPU::InternalRegisters@{ComSquare::CPU::InternalRegisters}}
\doxysubsubsection{\texorpdfstring{joy4h}{joy4h}}
{\footnotesize\ttfamily uint8\+\_\+t Com\+Square\+::\+C\+P\+U\+::\+Internal\+Registers\+::joy4h}



Controller Port Data \mbox{\hyperlink{structComSquare_1_1CPU_1_1Registers}{Registers}} (Pad 4 -\/ High) 

\mbox{\Hypertarget{structComSquare_1_1CPU_1_1InternalRegisters_a85afe00843e4f9616fa106c3ae610919}\label{structComSquare_1_1CPU_1_1InternalRegisters_a85afe00843e4f9616fa106c3ae610919}} 
\index{ComSquare::CPU::InternalRegisters@{ComSquare::CPU::InternalRegisters}!joy4l@{joy4l}}
\index{joy4l@{joy4l}!ComSquare::CPU::InternalRegisters@{ComSquare::CPU::InternalRegisters}}
\doxysubsubsection{\texorpdfstring{joy4l}{joy4l}}
{\footnotesize\ttfamily uint8\+\_\+t Com\+Square\+::\+C\+P\+U\+::\+Internal\+Registers\+::joy4l}



Controller Port Data \mbox{\hyperlink{structComSquare_1_1CPU_1_1Registers}{Registers}} (Pad 4 -\/ Low) 

\mbox{\Hypertarget{structComSquare_1_1CPU_1_1InternalRegisters_ab51577c6d3509770c1144e45932ee38c}\label{structComSquare_1_1CPU_1_1InternalRegisters_ab51577c6d3509770c1144e45932ee38c}} 
\index{ComSquare::CPU::InternalRegisters@{ComSquare::CPU::InternalRegisters}!mdmaen@{mdmaen}}
\index{mdmaen@{mdmaen}!ComSquare::CPU::InternalRegisters@{ComSquare::CPU::InternalRegisters}}
\doxysubsubsection{\texorpdfstring{mdmaen}{mdmaen}}
{\footnotesize\ttfamily uint8\+\_\+t Com\+Square\+::\+C\+P\+U\+::\+Internal\+Registers\+::mdmaen}



D\+MA Enable Register. 

\mbox{\Hypertarget{structComSquare_1_1CPU_1_1InternalRegisters_aa3dda181d78b6bcd50057d83c97ecb2c}\label{structComSquare_1_1CPU_1_1InternalRegisters_aa3dda181d78b6bcd50057d83c97ecb2c}} 
\index{ComSquare::CPU::InternalRegisters@{ComSquare::CPU::InternalRegisters}!memsel@{memsel}}
\index{memsel@{memsel}!ComSquare::CPU::InternalRegisters@{ComSquare::CPU::InternalRegisters}}
\doxysubsubsection{\texorpdfstring{memsel}{memsel}}
{\footnotesize\ttfamily uint8\+\_\+t Com\+Square\+::\+C\+P\+U\+::\+Internal\+Registers\+::memsel}



R\+OM Speed Register. 

\mbox{\Hypertarget{structComSquare_1_1CPU_1_1InternalRegisters_a45c471c6c5cef4d6a117e223b8a19ed1}\label{structComSquare_1_1CPU_1_1InternalRegisters_a45c471c6c5cef4d6a117e223b8a19ed1}} 
\index{ComSquare::CPU::InternalRegisters@{ComSquare::CPU::InternalRegisters}!nmitimen@{nmitimen}}
\index{nmitimen@{nmitimen}!ComSquare::CPU::InternalRegisters@{ComSquare::CPU::InternalRegisters}}
\doxysubsubsection{\texorpdfstring{nmitimen}{nmitimen}}
{\footnotesize\ttfamily uint8\+\_\+t Com\+Square\+::\+C\+P\+U\+::\+Internal\+Registers\+::nmitimen}



Interrupt Enable Register. 

\mbox{\Hypertarget{structComSquare_1_1CPU_1_1InternalRegisters_a70602e356a792a14a1b638d692556e8c}\label{structComSquare_1_1CPU_1_1InternalRegisters_a70602e356a792a14a1b638d692556e8c}} 
\index{ComSquare::CPU::InternalRegisters@{ComSquare::CPU::InternalRegisters}!rddivh@{rddivh}}
\index{rddivh@{rddivh}!ComSquare::CPU::InternalRegisters@{ComSquare::CPU::InternalRegisters}}
\doxysubsubsection{\texorpdfstring{rddivh}{rddivh}}
{\footnotesize\ttfamily uint8\+\_\+t Com\+Square\+::\+C\+P\+U\+::\+Internal\+Registers\+::rddivh}



Divide Result \mbox{\hyperlink{structComSquare_1_1CPU_1_1Registers}{Registers}} (can sometimes be used as multiplication result register) -\/ H\+I\+GH. 

\mbox{\Hypertarget{structComSquare_1_1CPU_1_1InternalRegisters_a18401a7dbfe4784b6367623cac251a5e}\label{structComSquare_1_1CPU_1_1InternalRegisters_a18401a7dbfe4784b6367623cac251a5e}} 
\index{ComSquare::CPU::InternalRegisters@{ComSquare::CPU::InternalRegisters}!rddivl@{rddivl}}
\index{rddivl@{rddivl}!ComSquare::CPU::InternalRegisters@{ComSquare::CPU::InternalRegisters}}
\doxysubsubsection{\texorpdfstring{rddivl}{rddivl}}
{\footnotesize\ttfamily uint8\+\_\+t Com\+Square\+::\+C\+P\+U\+::\+Internal\+Registers\+::rddivl}



Divide Result \mbox{\hyperlink{structComSquare_1_1CPU_1_1Registers}{Registers}} (can sometimes be used as multiplication result register) -\/ L\+OW. 

\mbox{\Hypertarget{structComSquare_1_1CPU_1_1InternalRegisters_acd1644bf64088f00ebeb2d62fe90fbe2}\label{structComSquare_1_1CPU_1_1InternalRegisters_acd1644bf64088f00ebeb2d62fe90fbe2}} 
\index{ComSquare::CPU::InternalRegisters@{ComSquare::CPU::InternalRegisters}!rdio@{rdio}}
\index{rdio@{rdio}!ComSquare::CPU::InternalRegisters@{ComSquare::CPU::InternalRegisters}}
\doxysubsubsection{\texorpdfstring{rdio}{rdio}}
{\footnotesize\ttfamily uint8\+\_\+t Com\+Square\+::\+C\+P\+U\+::\+Internal\+Registers\+::rdio}



IO Port Read Register. 

\mbox{\Hypertarget{structComSquare_1_1CPU_1_1InternalRegisters_a79c946893be3148b0c72d9da2c8f3428}\label{structComSquare_1_1CPU_1_1InternalRegisters_a79c946893be3148b0c72d9da2c8f3428}} 
\index{ComSquare::CPU::InternalRegisters@{ComSquare::CPU::InternalRegisters}!rdmpyh@{rdmpyh}}
\index{rdmpyh@{rdmpyh}!ComSquare::CPU::InternalRegisters@{ComSquare::CPU::InternalRegisters}}
\doxysubsubsection{\texorpdfstring{rdmpyh}{rdmpyh}}
{\footnotesize\ttfamily uint8\+\_\+t Com\+Square\+::\+C\+P\+U\+::\+Internal\+Registers\+::rdmpyh}



Multiplication Result \mbox{\hyperlink{structComSquare_1_1CPU_1_1Registers}{Registers}} (can sometimes be used as divide result register) -\/ H\+I\+GH. 

\mbox{\Hypertarget{structComSquare_1_1CPU_1_1InternalRegisters_a87261625195bb3f38db9354a29334ddf}\label{structComSquare_1_1CPU_1_1InternalRegisters_a87261625195bb3f38db9354a29334ddf}} 
\index{ComSquare::CPU::InternalRegisters@{ComSquare::CPU::InternalRegisters}!rdmpyl@{rdmpyl}}
\index{rdmpyl@{rdmpyl}!ComSquare::CPU::InternalRegisters@{ComSquare::CPU::InternalRegisters}}
\doxysubsubsection{\texorpdfstring{rdmpyl}{rdmpyl}}
{\footnotesize\ttfamily uint8\+\_\+t Com\+Square\+::\+C\+P\+U\+::\+Internal\+Registers\+::rdmpyl}



Multiplication Result \mbox{\hyperlink{structComSquare_1_1CPU_1_1Registers}{Registers}} (can sometimes be used as divide result register) -\/ L\+OW. 

\mbox{\Hypertarget{structComSquare_1_1CPU_1_1InternalRegisters_ac49c0aaf5eb44afe572930b1bfe13c00}\label{structComSquare_1_1CPU_1_1InternalRegisters_ac49c0aaf5eb44afe572930b1bfe13c00}} 
\index{ComSquare::CPU::InternalRegisters@{ComSquare::CPU::InternalRegisters}!rdnmi@{rdnmi}}
\index{rdnmi@{rdnmi}!ComSquare::CPU::InternalRegisters@{ComSquare::CPU::InternalRegisters}}
\doxysubsubsection{\texorpdfstring{rdnmi}{rdnmi}}
{\footnotesize\ttfamily uint8\+\_\+t Com\+Square\+::\+C\+P\+U\+::\+Internal\+Registers\+::rdnmi}



Interrupt Flag \mbox{\hyperlink{structComSquare_1_1CPU_1_1Registers}{Registers}}. 

\mbox{\Hypertarget{structComSquare_1_1CPU_1_1InternalRegisters_a0058417dd2f115ffd67c909b227552f8}\label{structComSquare_1_1CPU_1_1InternalRegisters_a0058417dd2f115ffd67c909b227552f8}} 
\index{ComSquare::CPU::InternalRegisters@{ComSquare::CPU::InternalRegisters}!timeup@{timeup}}
\index{timeup@{timeup}!ComSquare::CPU::InternalRegisters@{ComSquare::CPU::InternalRegisters}}
\doxysubsubsection{\texorpdfstring{timeup}{timeup}}
{\footnotesize\ttfamily uint8\+\_\+t Com\+Square\+::\+C\+P\+U\+::\+Internal\+Registers\+::timeup}



Interrupt Flag \mbox{\hyperlink{structComSquare_1_1CPU_1_1Registers}{Registers}} -\/ Time\+Up. 

\mbox{\Hypertarget{structComSquare_1_1CPU_1_1InternalRegisters_a24e773242680bd43e8d6a0fcd2e1ea48}\label{structComSquare_1_1CPU_1_1InternalRegisters_a24e773242680bd43e8d6a0fcd2e1ea48}} 
\index{ComSquare::CPU::InternalRegisters@{ComSquare::CPU::InternalRegisters}!vtimeh@{vtimeh}}
\index{vtimeh@{vtimeh}!ComSquare::CPU::InternalRegisters@{ComSquare::CPU::InternalRegisters}}
\doxysubsubsection{\texorpdfstring{vtimeh}{vtimeh}}
{\footnotesize\ttfamily uint8\+\_\+t Com\+Square\+::\+C\+P\+U\+::\+Internal\+Registers\+::vtimeh}



I\+RQ Timer \mbox{\hyperlink{structComSquare_1_1CPU_1_1Registers}{Registers}} (Vertical -\/ High) 

\mbox{\Hypertarget{structComSquare_1_1CPU_1_1InternalRegisters_a6262d0ba292853c4232d24b6142e1acf}\label{structComSquare_1_1CPU_1_1InternalRegisters_a6262d0ba292853c4232d24b6142e1acf}} 
\index{ComSquare::CPU::InternalRegisters@{ComSquare::CPU::InternalRegisters}!vtimel@{vtimel}}
\index{vtimel@{vtimel}!ComSquare::CPU::InternalRegisters@{ComSquare::CPU::InternalRegisters}}
\doxysubsubsection{\texorpdfstring{vtimel}{vtimel}}
{\footnotesize\ttfamily uint8\+\_\+t Com\+Square\+::\+C\+P\+U\+::\+Internal\+Registers\+::vtimel}



I\+RQ Timer \mbox{\hyperlink{structComSquare_1_1CPU_1_1Registers}{Registers}} (Vertical -\/ Low) 

\mbox{\Hypertarget{structComSquare_1_1CPU_1_1InternalRegisters_aa1466fa14182549898886e3eb3074f36}\label{structComSquare_1_1CPU_1_1InternalRegisters_aa1466fa14182549898886e3eb3074f36}} 
\index{ComSquare::CPU::InternalRegisters@{ComSquare::CPU::InternalRegisters}!wrdivb@{wrdivb}}
\index{wrdivb@{wrdivb}!ComSquare::CPU::InternalRegisters@{ComSquare::CPU::InternalRegisters}}
\doxysubsubsection{\texorpdfstring{wrdivb}{wrdivb}}
{\footnotesize\ttfamily uint8\+\_\+t Com\+Square\+::\+C\+P\+U\+::\+Internal\+Registers\+::wrdivb}



Divisor \& Dividend \mbox{\hyperlink{structComSquare_1_1CPU_1_1Registers}{Registers}} (B) 

\mbox{\Hypertarget{structComSquare_1_1CPU_1_1InternalRegisters_aa315eec822cf92ec586c2ba918a36e00}\label{structComSquare_1_1CPU_1_1InternalRegisters_aa315eec822cf92ec586c2ba918a36e00}} 
\index{ComSquare::CPU::InternalRegisters@{ComSquare::CPU::InternalRegisters}!wrdivh@{wrdivh}}
\index{wrdivh@{wrdivh}!ComSquare::CPU::InternalRegisters@{ComSquare::CPU::InternalRegisters}}
\doxysubsubsection{\texorpdfstring{wrdivh}{wrdivh}}
{\footnotesize\ttfamily uint8\+\_\+t Com\+Square\+::\+C\+P\+U\+::\+Internal\+Registers\+::wrdivh}



Divisor \& Dividend \mbox{\hyperlink{structComSquare_1_1CPU_1_1Registers}{Registers}} (A -\/ High) 

\mbox{\Hypertarget{structComSquare_1_1CPU_1_1InternalRegisters_ae98022af2fc7c80062444e9cecf95f0e}\label{structComSquare_1_1CPU_1_1InternalRegisters_ae98022af2fc7c80062444e9cecf95f0e}} 
\index{ComSquare::CPU::InternalRegisters@{ComSquare::CPU::InternalRegisters}!wrdivl@{wrdivl}}
\index{wrdivl@{wrdivl}!ComSquare::CPU::InternalRegisters@{ComSquare::CPU::InternalRegisters}}
\doxysubsubsection{\texorpdfstring{wrdivl}{wrdivl}}
{\footnotesize\ttfamily uint8\+\_\+t Com\+Square\+::\+C\+P\+U\+::\+Internal\+Registers\+::wrdivl}



Divisor \& Dividend \mbox{\hyperlink{structComSquare_1_1CPU_1_1Registers}{Registers}} (A -\/ Low) 

\mbox{\Hypertarget{structComSquare_1_1CPU_1_1InternalRegisters_afac8a1b505dff6a6aa9416392e469471}\label{structComSquare_1_1CPU_1_1InternalRegisters_afac8a1b505dff6a6aa9416392e469471}} 
\index{ComSquare::CPU::InternalRegisters@{ComSquare::CPU::InternalRegisters}!wrio@{wrio}}
\index{wrio@{wrio}!ComSquare::CPU::InternalRegisters@{ComSquare::CPU::InternalRegisters}}
\doxysubsubsection{\texorpdfstring{wrio}{wrio}}
{\footnotesize\ttfamily uint8\+\_\+t Com\+Square\+::\+C\+P\+U\+::\+Internal\+Registers\+::wrio}



IO Port Write Register. 

\mbox{\Hypertarget{structComSquare_1_1CPU_1_1InternalRegisters_a0ec804218ae29f8ad4b8019dd78dc38f}\label{structComSquare_1_1CPU_1_1InternalRegisters_a0ec804218ae29f8ad4b8019dd78dc38f}} 
\index{ComSquare::CPU::InternalRegisters@{ComSquare::CPU::InternalRegisters}!wrmpya@{wrmpya}}
\index{wrmpya@{wrmpya}!ComSquare::CPU::InternalRegisters@{ComSquare::CPU::InternalRegisters}}
\doxysubsubsection{\texorpdfstring{wrmpya}{wrmpya}}
{\footnotesize\ttfamily uint8\+\_\+t Com\+Square\+::\+C\+P\+U\+::\+Internal\+Registers\+::wrmpya}



Multiplicand Register A. 

\mbox{\Hypertarget{structComSquare_1_1CPU_1_1InternalRegisters_a258f0d486b05d1d77f39b3c10f6eaaf5}\label{structComSquare_1_1CPU_1_1InternalRegisters_a258f0d486b05d1d77f39b3c10f6eaaf5}} 
\index{ComSquare::CPU::InternalRegisters@{ComSquare::CPU::InternalRegisters}!wrmpyb@{wrmpyb}}
\index{wrmpyb@{wrmpyb}!ComSquare::CPU::InternalRegisters@{ComSquare::CPU::InternalRegisters}}
\doxysubsubsection{\texorpdfstring{wrmpyb}{wrmpyb}}
{\footnotesize\ttfamily uint8\+\_\+t Com\+Square\+::\+C\+P\+U\+::\+Internal\+Registers\+::wrmpyb}



Multiplicand Register B. 



The documentation for this struct was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
sources/\+C\+P\+U/\mbox{\hyperlink{CPU_8hpp}{C\+P\+U.\+hpp}}\end{DoxyCompactItemize}
