mirror of
https://github.com/zoriya/ComSquare.git
synced 2026-06-01 09:45:25 +00:00
Replace logger with basic disassembly in APU debugger (& fixing Absolute By X Address operand?)
This commit is contained in:
Melefo
@@ -11,8 +11,301 @@
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namespace ComSquare::Debugger
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{
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class APUDebug : public APU::APU, public QObject {
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//! @brief List of all types of operands used by the instructions
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enum Operand
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{
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None,
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A,
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X,
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Y,
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SP,
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PSW,
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ImmediateData,
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IndexXAddr,
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IndexYAddr,
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AbsoluteBit,
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AbsoluteAddr,
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AbsoluteAddrByX,
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AbsoluteAddrByY,
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AbsoluteByXAddr,
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AbsoluteDirectByXAddr,
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AbsoluteDirectAddrByY,
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DirectAddr,
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DirectAddrByX,
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DirectAddrByY
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};
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//! @brief Small structure to store some values on the instructions
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struct Instruction
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{
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std::string name;
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int size;
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std::tuple<Operand, Operand> operands;
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};
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class APUDebug : public APU::APU, public QObject
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{
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private:
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//! @brief List of instructions and their information
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std::array<Instruction, 0x100> _instructions {{
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{"NOP", 1, {None, None}},
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{"TCALL", 1, {None, None}},
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{"SET1", 2, {DirectAddr, None}},
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{"BBS", 3, {DirectAddr, ImmediateData}},
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{"OR", 2, {DirectAddr, None}},
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{"OR", 3, {AbsoluteAddr, None}},
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{"OR", 1, {IndexXAddr, None}},
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{"OR", 2, {AbsoluteDirectByXAddr, None}},
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{"OR", 2, {ImmediateData, None}},
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{"OR", 3, {DirectAddr, DirectAddr}},
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{"OR1", 3, {AbsoluteBit, None}},
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{"ASL", 2, {DirectAddr, None}},
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{"ASL", 3, {AbsoluteAddr, None}},
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{"PUSH", 1, {PSW, None}},
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{"TSET1", 3, {AbsoluteAddr, None}},
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{"BRK", 1, {None, None}},
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{"BPL", 2, {ImmediateData, None}},
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{"TCALL", 1, {None, None}},
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{"CLR1", 2, {DirectAddr, None}},
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{"BBC", 3, {DirectAddr, ImmediateData}},
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{"OR", 2, {DirectAddrByX, None}},
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{"OR", 3, {AbsoluteAddrByX, None}},
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{"OR", 3, {AbsoluteAddrByY, None}},
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{"OR", 2, {AbsoluteDirectAddrByY, None}},
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{"OR", 3, {DirectAddr, ImmediateData}},
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{"OR", 1, {IndexYAddr, IndexYAddr}},
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{"DECW", 2, {DirectAddr, None}},
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{"ASL", 2, {DirectAddrByX, None}},
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{"ASL", 1, {A, None}},
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{"DEC", 1, {X, None}},
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{"CMP", 3, {X, AbsoluteAddr}},
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{"JMP", 3, {AbsoluteByXAddr, None}},
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{"CLRP", 1, {None, None}},
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{"TCALL", 1, {None, None}},
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{"SET1", 2, {DirectAddr, None}},
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{"BBS", 3, {DirectAddr, ImmediateData}},
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{"AND", 2, {DirectAddr, None}},
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{"AND", 3, {AbsoluteAddr, None}},
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{"AND", 1, {IndexXAddr, None}},
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{"AND", 2, {AbsoluteDirectByXAddr, None}},
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{"AND", 2, {ImmediateData, None}},
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{"AND", 3, {DirectAddr, DirectAddr}},
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{"OR1", 3, {AbsoluteBit, None}},
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{"ROL", 2, {DirectAddr, None}},
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{"ROL", 3, {AbsoluteAddr, None}},
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{"PUSH", 1, {A, None}},
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{"CBNE", 3, {ImmediateData, ImmediateData}},
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{"BRA", 2, {ImmediateData, None}},
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{"BMI", 2, {ImmediateData, None}},
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{"TCALL", 1, {None, None}},
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{"CLR1", 2, {DirectAddr, None}},
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{"BBC", 3, {DirectAddr, ImmediateData}},
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{"AND", 2, {DirectAddrByX, None}},
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{"AND", 3, {AbsoluteAddrByX, None}},
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{"AND", 3, {AbsoluteAddrByY, None}},
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{"AND", 2, {AbsoluteDirectAddrByY, None}},
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{"AND", 3, {DirectAddr, ImmediateData}},
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{"AND", 1, {IndexXAddr, IndexYAddr}},
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{"INCW", 2, {DirectAddr, None}},
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{"ROL", 2, {AbsoluteAddrByX, None}},
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{"ROL", 1, {A, None}},
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{"INC", 1, {X, None}},
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{"CMP", 2, {X, DirectAddr}},
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{"CALL", 3, {AbsoluteAddr, None}},
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{"SETP", 1, {None, None}},
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{"TCALL", 1, {None, None}},
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{"SET1", 2, {DirectAddr, None}},
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{"BBS", 3, {DirectAddr, ImmediateData}},
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{"EOR", 2, {DirectAddr, None}},
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{"EOR", 3, {AbsoluteAddr, None}},
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{"EOR", 1, {IndexXAddr, None}},
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{"EOR", 2, {AbsoluteDirectByXAddr, None}},
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{"EOR", 2, {ImmediateData, None}},
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{"EOR", 3, {DirectAddr, DirectAddr}},
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{"AND1", 3, {AbsoluteBit, None}},
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{"LSR", 2, {DirectAddr, None}},
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{"LSR", 3, {AbsoluteAddr, None}},
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{"PUSH", 1, {X, None}},
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{"TCLR1", 3, {AbsoluteAddr, None}},
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{"PCALL", 3, {None, None}},
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{"BVC", 2, {ImmediateData, None}},
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{"TCALL", 1, {None, None}},
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{"CLR1", 2, {DirectAddr, None}},
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{"BBC", 3, {DirectAddr, ImmediateData}},
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{"EOR", 2, {DirectAddrByX, None}},
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{"EOR", 3, {AbsoluteAddrByX, None}},
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{"EOR", 3, {AbsoluteAddrByY, None}},
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{"EOR", 2, {AbsoluteDirectAddrByY, None}},
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{"EOR", 3, {DirectAddr, ImmediateData}},
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{"EOR", 1, {IndexXAddr, IndexYAddr}},
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{"CMPW", 2, {DirectAddr, None}},
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{"LSR", 2, {DirectAddrByX, None}},
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{"LSR", 1, {A, None}},
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{"MOV", 1, {A, X}},
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{"CMP", 3, {Y, AbsoluteAddr}},
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{"JMP", 3, {AbsoluteAddr, None}},
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{"CLRC", 1, {None, None}},
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{"TCALL", 1, {None, None}},
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{"SET1", 2, {DirectAddr, None}},
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{"BBS", 3, {DirectAddr, ImmediateData}},
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{"CMP", 2, {A, DirectAddr}},
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{"CMP", 3, {A, AbsoluteAddr}},
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{"CMP", 1, {A, IndexXAddr,}},
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{"CMP", 2, {A, AbsoluteDirectByXAddr}},
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{"CMP", 2, {A, ImmediateData}},
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{"CMP", 3, {DirectAddr, DirectAddr}},
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{"AND1", 3, {AbsoluteBit, None}},
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{"ROR", 2, {DirectAddr , None}},
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{"ROR", 3, {AbsoluteAddr, None}},
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{"PUSH", 1, {Y, None}},
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{"DBNZ", 3, {ImmediateData, None}},
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{"RET", 1, {None, None}},
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{"BVS", 2, {ImmediateData, None}},
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{"TCALL", 1, {None, None}},
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{"CLR1", 2, {DirectAddr, None}},
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{"BBC", 3, {DirectAddr, ImmediateData}},
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{"CMP", 2, {A, DirectAddrByX}},
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{"CMP", 3, {A, AbsoluteAddrByX}},
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{"CMP", 3, {A, AbsoluteAddrByY}},
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{"CMP", 2, {A, AbsoluteDirectAddrByY}},
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{"CMP", 3, {DirectAddr, ImmediateData}},
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{"CMP", 1, {IndexXAddr, IndexYAddr}},
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{"ADDW", 2, {DirectAddr, None}},
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{"ROR", 2, {DirectAddrByX, None}},
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{"ROR", 1, {A, None}},
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{"MOV", 1, {X, A}},
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{"CMP", 3, {Y, DirectAddr}},
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{"RETI", 1, {None, None}},
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{"SETC", 1, {None, None}},
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{"TCALL", 1, {None, None}},
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{"SET1", 2, {DirectAddr, None}},
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{"BBS", 3, {DirectAddr, ImmediateData}},
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{"ADC", 2, {DirectAddr, None}},
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{"ADC", 3, {AbsoluteAddr, None}},
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{"ADC", 1, {IndexXAddr, None}},
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{"ADC", 2, {AbsoluteDirectByXAddr, None}},
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{"ADC", 2, {ImmediateData, None}},
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{"ADC", 3, {DirectAddr, DirectAddr}},
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{"EOR1", 3, {AbsoluteBit, None}},
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{"DEC", 2, {DirectAddr, None}},
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{"DEC", 3, {AbsoluteAddr, None}},
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{"MOV", 2, {ImmediateData, Y}},
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{"POP", 1, {PSW, None}},
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{"MOV", 3, {DirectAddr, ImmediateData}},
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{"BCC", 2, {ImmediateData, None}},
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{"TCALL", 1, {None, None}},
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{"CLR1", 2, {DirectAddr, None}},
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{"BBC", 3, {DirectAddr, ImmediateData}},
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{"ADC", 2, {DirectAddrByX, None}},
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{"ADC", 3, {AbsoluteAddrByX, None}},
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{"ADC", 3, {AbsoluteAddrByY, None}},
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{"ADC", 2, {AbsoluteDirectAddrByY, None}},
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{"ADC", 3, {DirectAddr, ImmediateData}},
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{"ADC", 1, {IndexXAddr, IndexYAddr}},
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{"SUBW", 2, {DirectAddr, None}},
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{"DEC", 2, {DirectAddrByX, None}},
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{"DEC", 1, {A, None}},
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{"MOV", 1, {SP, X}},
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{"DIV", 1, {None, None}},
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{"XCN", 1, {None, None}},
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{"EI", 1, {None, None}},
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{"TCALL", 1, {None, None}},
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{"SET1", 2, {DirectAddr, None}},
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{"BBS", 3, {DirectAddr, ImmediateData}},
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{"SBC", 2, {DirectAddr, None}},
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{"SBC", 3, {AbsoluteAddr, None}},
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{"SBC", 1, {IndexXAddr, None}},
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{"SBC", 2, {AbsoluteDirectByXAddr, None}},
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{"SBC", 2, {ImmediateData, None}},
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{"SBC", 3, {DirectAddr, DirectAddr}},
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{"MOV1", 3, {AbsoluteBit, None}},
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{"INC", 2, {DirectAddr, None}},
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{"INC", 3, {AbsoluteAddr, None}},
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{"CMP", 2, {Y, ImmediateData}},
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{"POP", 1, {A, None}},
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{"MOV", 1, {A, IndexXAddr}},
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{"BCS", 2, {ImmediateData, None}},
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{"TCALL", 1, {None, None}},
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{"CLR1", 2, {DirectAddr, None}},
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{"BBC", 3, {DirectAddr, ImmediateData}},
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{"SBC", 2, {DirectAddrByX, None}},
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{"SBC", 3, {AbsoluteAddrByX, None}},
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{"SBC", 3, {AbsoluteAddrByY, None}},
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{"SBC", 2, {AbsoluteDirectAddrByY, None}},
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{"SBC", 2, {DirectAddr, ImmediateData}},
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{"SBC", 1, {IndexXAddr, IndexYAddr}},
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{"MOVW", 2, {DirectAddr, None}},
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{"INC", 2, {DirectAddrByX, None}},
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{"INC", 1, {A, None}},
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{"MOV", 1, {X, SP}},
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{"DAS", 1, {None, None}},
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{"MOV", 1, {IndexXAddr, A}},
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{"DI", 1, {None, None}},
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{"TCALL", 1, {None, None}},
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{"SET1", 2, {DirectAddr, None}},
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{"BBS", 3, {DirectAddr, ImmediateData}},
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{"MOV", 2, {A, DirectAddr}},
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{"MOV", 3, {A, AbsoluteAddr}},
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{"MOV", 1, {A, IndexXAddr}},
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{"MOV", 2, {A, AbsoluteDirectByXAddr}},
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{"CMP", 2, {X, ImmediateData}},
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{"MOV", 3, {X, AbsoluteAddr}},
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{"MOV1", 3, {AbsoluteBit, None}},
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{"MOV", 2, {Y, DirectAddr}},
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{"MOV", 3, {Y, AbsoluteAddr}},
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{"MOV", 2, {ImmediateData, X}},
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{"POP", 1, {X, None}},
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{"MUL", 1, {None, None}},
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{"BNE", 2, {ImmediateData, None}},
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{"TCALL", 1, {None, None}},
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{"CLR1", 2, {DirectAddr, None}},
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{"BBC", 3, {DirectAddr, ImmediateData}},
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{"MOV", 2, {A, DirectAddrByX}},
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{"MOV", 3, {A, AbsoluteAddrByX}},
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{"MOV", 3, {A, AbsoluteAddrByY}},
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{"MOV", 2, {A, AbsoluteDirectAddrByY}},
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{"MOV", 2, {X, DirectAddr}},
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{"MOV", 2, {X, DirectAddrByY}},
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{"MOVW", 2, {DirectAddr, None}},
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{"MOV", 2, {Y, DirectAddrByX}},
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{"DEC", 1, {Y, None}},
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{"MOV", 1, {Y, A}},
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{"CBNE", 3, {DirectAddrByX, ImmediateData}},
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{"DAA", 1, {None, None}},
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{"CLRV", 1, {None, None}},
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{"TCALL", 1, {None, None}},
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{"SET1", 2, {DirectAddr, None}},
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{"BBS", 3, {DirectAddr, ImmediateData}},
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{"MOV", 2, {DirectAddr, A}},
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{"MOV", 3, {AbsoluteAddrByX, A}},
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{"MOV", 1, {IndexXAddr, A}},
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{"MOV", 2, {AbsoluteDirectByXAddr, A}},
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{"MOV", 2, {ImmediateData, A}},
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{"MOV", 3, {AbsoluteAddr, X}},
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{"NOT1", 3, {AbsoluteBit, None}},
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{"MOV", 2, {DirectAddr, Y}},
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{"MOV", 3, {AbsoluteAddr, Y}},
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{"NOTC", 1, {None, None}},
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{"POP", 1, {Y, None}},
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{"SLEEP", 1, {None, None}},
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{"BEQ", 2, {ImmediateData, None}},
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{"TCALL", 1, {None, None}},
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{"CLR1", 2, {DirectAddr, None}},
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{"BBC", 3, {DirectAddr, ImmediateData}},
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{"MOV", 2, {DirectAddrByX, A}},
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{"MOV", 3, {AbsoluteAddrByX, A}},
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{"MOV", 3, {AbsoluteAddrByY, A}},
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{"MOV", 2, {AbsoluteDirectAddrByY, A}},
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{"MOV", 2, {DirectAddr, X}},
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{"MOV", 2, {DirectAddrByY, X}},
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{"MOV", 3, {DirectAddr, DirectAddr}},
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{"MOV", 2, {DirectAddrByX, Y}},
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{"INC", 1, {Y, None}},
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{"MOV", 1, {A, Y}},
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{"DBNZ", 3, {ImmediateData, None}},
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{"STOP", 1, {None, None}}
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}};
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//! @brief The QT window for this debugger.
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ClosableWindow<APUDebug> *_window;
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@@ -30,14 +323,18 @@ namespace ComSquare::Debugger
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//! @brief Update the debugger panel values
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void _updatePanel();
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//! @brief Convert CPU APU flags to a string.
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std::string _getPSWString();
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//! @brief Updates the object that serves as the disassembly
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void _updateLogger();
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//! @brief Replace original _executeInstruction to write to the logger.
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int _executeInstruction() override;
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//! @brief return the mnemonic of the current instruction done.
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std::string _getInstructionString();
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//! @brief Retrieves the instruction from the SP location
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Instruction &_getInstruction();
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//! @brief Returns an operand in text format
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std::string _getOperand(Operand ope);
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public slots:
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//! @brief Pause/Resume the APU.
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void pause();
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@@ -55,7 +352,6 @@ namespace ComSquare::Debugger
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//! @brief Override the apu's update to disable debugging.
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void update(unsigned cycles) override;
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//! @brief Return true if the CPU is overloaded with debugging features.
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bool isDebugger() const override;
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