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Implementing LSR

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This commit is contained in:
Anonymus Raccoon
2020-05-13 14:39:46 +02:00
parent 66f82dc5f0
commit 475986580d
3 changed files with 85 additions and 7 deletions
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sources/CPU/Instructions/BitsInstructions.cpp
+40 -2
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@@ -61,6 +61,7 @@ namespace ComSquare::CPU
unsigned highByte = this->_registers.p.m ? 0x80u : 0x8000u;
if (mode == Implied) {
this->_registers.p.c = this->_registers.a & highByte;
this->_registers.a <<= 1u;
this->_registers.p.n = this->_registers.a & highByte;
this->_registers.p.z = this->_registers.a == 0;
@@ -72,15 +73,52 @@ namespace ComSquare::CPU
value += this->_bus->read(valueAddr + 1) << 8u;
this->_registers.p.c = value & highByte;
value <<= 1u;
this->_registers.p.n = value & highByte;
this->_registers.p.z = value == 0;
this->_bus->write(valueAddr, value);
if (!this->_registers.p.m)
this->_bus->write(valueAddr + 1, value >> 8u);
this->_registers.p.n = value & highByte;
int cycles = 2 * !this->_registers.p.m;
switch (mode) {
case DirectPage:
case DirectPageIndexedByX:
cycles += this->_registers.dl != 0;
break;
case AbsoluteIndexedByX:
cycles += this->_hasIndexCrossedPageBoundary;
break;
default:
break;
}
return cycles;
}
int CPU::LSR(uint24_t valueAddr, AddressingMode mode)
{
this->_registers.p.n = false;
if (mode == Implied) {
this->_registers.p.c = this->_registers.a & 1u;
this->_registers.a >>= 1u;
this->_registers.p.z = this->_registers.a == 0;
return 0;
}
uint16_t value = this->_bus->read(valueAddr);
if (!this->_registers.p.m)
value += this->_bus->read(valueAddr + 1) << 8u;
this->_registers.p.c = value & 1u;
value >>= 1u;
this->_registers.p.z = value == 0;
this->_bus->write(valueAddr, value);
if (!this->_registers.p.m)
this->_bus->write(valueAddr + 1, value >> 8u);
int cycles = 2 * !this->_registers.p.m;
switch (mode) {
case DirectPage: