mirror of
https://github.com/zoriya/ComSquare.git
synced 2026-05-27 00:07:10 +00:00
Moving DSP in its own folder
Implementing read & write with all registers for DSP Replacing APU registers with internal registers and vice-versa Associate DSP with APU in constructor
This commit is contained in:
+27
-28
@@ -8,37 +8,36 @@
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namespace ComSquare::APU
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{
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APU::APU()
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{
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}
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APU::APU() : _dsp(new DSP::DSP)
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{ }
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uint8_t APU::read(uint24_t addr)
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{
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switch (addr) {
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case 0xF0:
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return this->_internalRegisters.unknown;
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return this->_registers.unknown;
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case 0xF2:
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return this->_internalRegisters.dspregAddr;
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return this->_registers.dspregAddr;
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case 0xF3:
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return this->_internalRegisters.dspregData;
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return this->_registers.dspregData;
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case 0xF4:
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return this->_internalRegisters.port0;
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return this->_registers.port0;
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case 0xF5:
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return this->_internalRegisters.port1;
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return this->_registers.port1;
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case 0xF6:
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return this->_internalRegisters.port2;
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return this->_registers.port2;
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case 0xF7:
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return this->_internalRegisters.port3;
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return this->_registers.port3;
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case 0xF8:
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return this->_internalRegisters.regmem1;
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return this->_registers.regmem1;
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case 0xF9:
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return this->_internalRegisters.regmem2;
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return this->_registers.regmem2;
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case 0xFD:
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return this->_internalRegisters.counter0;
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return this->_registers.counter0;
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case 0xFE:
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return this->_internalRegisters.counter1;
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return this->_registers.counter1;
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case 0xFF:
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return this->_internalRegisters.counter2;
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return this->_registers.counter2;
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default:
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throw InvalidAddress("APU Internal Registers read", addr);
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}
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@@ -48,43 +47,43 @@ namespace ComSquare::APU
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{
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switch (addr) {
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case 0xF0:
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this->_internalRegisters.unknown = data;
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this->_registers.unknown = data;
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break;
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case 0xF1:
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this->_internalRegisters.ctrlreg = data;
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this->_registers.ctrlreg = data;
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break;
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case 0xF2:
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this->_internalRegisters.dspregAddr = data;
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this->_registers.dspregAddr = data;
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break;
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case 0xF3:
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this->_internalRegisters.dspregData = data;
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this->_registers.dspregData = data;
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break;
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case 0xF4:
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this->_internalRegisters.port0 = data;
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this->_registers.port0 = data;
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break;
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case 0xF5:
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this->_internalRegisters.port1 = data;
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this->_registers.port1 = data;
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break;
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case 0xF6:
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this->_internalRegisters.port2 = data;
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this->_registers.port2 = data;
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break;
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case 0xF7:
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this->_internalRegisters.port3 = data;
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this->_registers.port3 = data;
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break;
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case 0xF8:
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this->_internalRegisters.regmem1 = data;
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this->_registers.regmem1 = data;
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break;
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case 0xF9:
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this->_internalRegisters.regmem2 = data;
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this->_registers.regmem2 = data;
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break;
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case 0xFA:
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this->_internalRegisters.timer0 = data;
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this->_registers.timer0 = data;
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break;
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case 0xFB:
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this->_internalRegisters.timer1 = data;
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this->_registers.timer1 = data;
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break;
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case 0xFC:
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this->_internalRegisters.timer2 = data;
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this->_registers.timer2 = data;
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break;
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default:
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throw InvalidAddress("APU Internal Registers write", addr);
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