Implementing the INC

This commit is contained in:
Anonymus Raccoon
2020-04-06 17:59:25 +02:00
parent 724a2ca616
commit 5ded0b44e8
3 changed files with 114 additions and 6 deletions
@@ -254,7 +254,7 @@ namespace ComSquare::CPU
int CPU::AND(uint24_t valueAddr, AddressingMode mode)
{
unsigned negativeMask = this->_isEmulationMode ? 0x80u : 0x8000u;
unsigned negativeMask = this->_registers.p.m ? 0x80u : 0x8000u;
unsigned value = this->_bus->read(valueAddr);
if (!this->_registers.p.m)
value += this->_bus->read(valueAddr + 1) << 8u;
@@ -285,4 +285,44 @@ namespace ComSquare::CPU
}
return cycles;
}
int CPU::INC(uint24_t valueAddr, AddressingMode mode)
{
unsigned negativeMask = this->_registers.p.m ? 0x80u : 0x8000u;
unsigned result;
if (mode == Implied) {
this->_registers.a++;
if (this->_registers.p.m)
this->_registers.ah = 0;
result = this->_registers.a;
} else if (!this->_registers.p.m) {
result = this->_bus->read(valueAddr);
result += this->_bus->read(valueAddr + 1) << 8u;
result = (uint16_t)(result + 1);
this->_bus->write(valueAddr, result);
this->_bus->write(valueAddr + 1, result << 8u);
} else {
result = this->_bus->read(valueAddr);
result = (uint8_t)(result + 1);
this->_bus->write(valueAddr, result);
}
this->_registers.p.z = result == 0;
this->_registers.p.n = result & negativeMask;
switch (mode) {
case Implied:
return 0;
case Absolute:
return this->_registers.p.m == 0 ? 2 : 0;
case DirectPage:
case DirectPageIndexedByX:
return (this->_registers.p.m == 0 ? 2 : 0) + this->_registers.dl != 0 ;
case AbsoluteIndexedByX:
return (this->_registers.p.m == 0 ? 2 : 0) + this->_hasIndexCrossedPageBoundary;
default:
return 0;
}
}
}