From 7fe28a8bcc75ba62dcb2d33f3d6216e3680dbb21 Mon Sep 17 00:00:00 2001
From: Anonymus Raccoon <tr.tristan-roux@outlook.fr>
Date: Wed, 13 May 2020 19:14:53 +0200
Subject: [PATCH] Implemnting the STP

---
 sources/CPU/CPU.cpp                              | 2 ++
 sources/CPU/CPU.hpp                              | 6 +++++-
 sources/CPU/Instructions/InternalInstruction.cpp | 6 ++++++
 sources/CPU/Instructions/Interrupts.cpp          | 1 +
 4 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/sources/CPU/CPU.cpp b/sources/CPU/CPU.cpp
index 7e3ba69..4f2a727 100644
--- a/sources/CPU/CPU.cpp
+++ b/sources/CPU/CPU.cpp
@@ -205,6 +205,8 @@ namespace ComSquare::CPU
 	{
 		unsigned cycles = 0;
 
+		if (this->_isStopped)
+			return 0xFF;
 		for (int i = 0; i < 0xFF; i++)
 			cycles += this->_executeInstruction(this->readPC());
 		return cycles;
diff --git a/sources/CPU/CPU.hpp b/sources/CPU/CPU.hpp
index a4746a3..1baa090 100644
--- a/sources/CPU/CPU.hpp
+++ b/sources/CPU/CPU.hpp
@@ -188,6 +188,8 @@ namespace ComSquare::CPU
 		Registers _registers{};
 		//! @brief Is the CPU running in emulation mode (in 8bits)
 		bool _isEmulationMode = true;
+		//! @brief If the processor is stopped (using an STP instruction), the clock is stopped and no instruction will be run until a manual reset.
+		bool _isStopped = false;
 		//! @brief Internal registers of the CPU (accessible from the bus via addr $4200 to $421F).
 		InternalRegisters _internalRegisters{};
 		//! @brief The memory bus to use for read/write.
@@ -439,6 +441,8 @@ namespace ComSquare::CPU
 		int PEI(uint24_t, AddressingMode);
 		//! @brief Push Effective Absolute Address
 		int PEA(uint24_t, AddressingMode);
+		//! @brief Stop the processor
+		int STP(uint24_t, AddressingMode);
 
 		//! @brief All the instructions of the CPU.
 		//! @info Instructions are indexed by their opcode
@@ -662,7 +666,7 @@ namespace ComSquare::CPU
 			{&CPU::CLD, 2, "cld", AddressingMode::Implied, 2}, // D8
 			{&CPU::CMP, 4, "cmp", AddressingMode::AbsoluteIndexedByY, 3}, // D9
 			{&CPU::PHX, 3, "phx", AddressingMode::Implied, 1}, // DA
-			{&CPU::BRK, 7, "stp #-#", AddressingMode::Implied, 2}, // DB
+			{&CPU::STP, 3, "stp", AddressingMode::Implied, 1}, // DB
 			{&CPU::JML, 7, "jml", AddressingMode::AbsoluteIndirectLong, 2}, // DC
 			{&CPU::CMP, 4, "cmp", AddressingMode::AbsoluteIndexedByX, 3}, // DD
 			{&CPU::DEC, 7, "dec", AddressingMode::AbsoluteIndexedByX, 3}, // DE
diff --git a/sources/CPU/Instructions/InternalInstruction.cpp b/sources/CPU/Instructions/InternalInstruction.cpp
index bb06b87..59eddbc 100644
--- a/sources/CPU/Instructions/InternalInstruction.cpp
+++ b/sources/CPU/Instructions/InternalInstruction.cpp
@@ -320,4 +320,10 @@ namespace ComSquare::CPU
 		this->_registers.dbr = this->_pop();
 		return 0;
 	}
+
+	int CPU::STP(uint24_t, AddressingMode)
+	{
+		this->_isStopped = true;
+		return 0;
+	}
 }
\ No newline at end of file
diff --git a/sources/CPU/Instructions/Interrupts.cpp b/sources/CPU/Instructions/Interrupts.cpp
index 2e09647..8f8d515 100644
--- a/sources/CPU/Instructions/Interrupts.cpp
+++ b/sources/CPU/Instructions/Interrupts.cpp
@@ -18,6 +18,7 @@ namespace ComSquare::CPU
 		this->_registers.d = 0x0000;
 		this->_registers.sh = 0x01; // the low bit of the stack pointer is undefined on reset.
 		this->_registers.pc = this->_cartridgeHeader.emulationInterrupts.reset;
+		this->_isStopped = false;
 		return 0;
 	}