diff --git a/sources/CPU/CPU.cpp b/sources/CPU/CPU.cpp
index 6e20259..7402b31 100644
--- a/sources/CPU/CPU.cpp
+++ b/sources/CPU/CPU.cpp
@@ -236,9 +236,18 @@ namespace ComSquare::CPU
 		case Instructions::STA_SR:   this->STA(this->_getStackRelativeAddr()); 					return 4 + !this->_registers.p.m;
 		case Instructions::STA_SRYi: this->STA(this->_getStackRelativeIndirectIndexedYAddr()); 	return 7 + !this->_registers.p.m;
 
-		case Instructions::STX_ABS:  this->STX(this->_getAbsoluteAddr()); 	return 4 + !this->_registers.p.m;
-		case Instructions::STX_DP:  this->STX(this->_getAbsoluteAddr()); 		return 3 + !this->_registers.p.m + this->_registers.dl != 0;
-		case Instructions::STX_DPY:  this->STX(this->_getAbsoluteAddr());		return 4 + !this->_registers.p.m + this->_registers.dl != 0;
+		case Instructions::STX_ABS:  this->STX(this->_getAbsoluteAddr()); 		return 4 + !this->_registers.p.m;
+		case Instructions::STX_DP:   this->STX(this->_getDirectAddr()); 			return 3 + !this->_registers.p.m + this->_registers.dl != 0;
+		case Instructions::STX_DPY:  this->STX(this->_getDirectIndexedByYAddr());	return 4 + !this->_registers.p.m + this->_registers.dl != 0;
+
+		case Instructions::STY_ABS:  this->STX(this->_getAbsoluteAddr()); 		return 4 + !this->_registers.p.m;
+		case Instructions::STY_DP:   this->STX(this->_getDirectAddr()); 			return 3 + !this->_registers.p.m + this->_registers.dl != 0;
+		case Instructions::STY_DPX:  this->STX(this->_getDirectIndexedByXAddr());	return 4 + !this->_registers.p.m + this->_registers.dl != 0;
+
+		case Instructions::STZ_ABS:  this->STX(this->_getAbsoluteAddr()); 			return 4 + !this->_registers.p.m;
+		case Instructions::STZ_DP:   this->STX(this->_getDirectAddr()); 				return 3 + !this->_registers.p.m + this->_registers.dl != 0;
+		case Instructions::STZ_ABSX: this->STX(this->_getAbsoluteIndexedByXAddr()); 	return 3 + !this->_registers.p.m + this->_registers.dl != 0;
+		case Instructions::STZ_DPX:  this->STX(this->_getDirectIndexedByXAddr());		return 4 + !this->_registers.p.m + this->_registers.dl != 0;
 
 		default:
 			throw InvalidOpcode("CPU", opcode);
diff --git a/sources/CPU/CPU.hpp b/sources/CPU/CPU.hpp
index 4c9a3e0..b68ef34 100644
--- a/sources/CPU/CPU.hpp
+++ b/sources/CPU/CPU.hpp
@@ -222,7 +222,16 @@ namespace ComSquare::CPU
 
 		STX_ABS = 0x8E,
 		STX_DP = 0x86,
-		STX_DPY = 0x96
+		STX_DPY = 0x96,
+
+		STY_ABS = 0x8C,
+		STY_DP = 0x84,
+		STY_DPX = 0x94,
+
+		STZ_ABS = 0x9C,
+		STZ_DP = 0x64,
+		STZ_ABSX = 0x9E,
+		STZ_DPX = 0x74
 	};
 
 	//! @brief The main CPU
@@ -311,6 +320,10 @@ namespace ComSquare::CPU
 		void STA(uint24_t addr);
 		//! @brief Store the index register X to memory.
 		void STX(uint24_t addr);
+		//! @brief Store the index register Y to memory.
+		void STY(uint24_t addr);
+		//! @brief Store zero to the memory.
+		void STZ(uint24_t addr);
 	public:
 		explicit CPU(std::shared_ptr<Memory::MemoryBus> bus, Cartridge::Header &cartridgeHeader);
 		//! @brief This function continue to execute the Cartridge code.
diff --git a/sources/CPU/Instructions/MemoryInstructions.cpp b/sources/CPU/Instructions/MemoryInstructions.cpp
index e8dce2c..348329e 100644
--- a/sources/CPU/Instructions/MemoryInstructions.cpp
+++ b/sources/CPU/Instructions/MemoryInstructions.cpp
@@ -25,4 +25,21 @@ namespace ComSquare::CPU
 			this->_bus->write(addr + 1, this->_registers.xh);
 		}
 	}
+
+	void CPU::STY(uint24_t addr)
+	{
+		if (this->_registers.p.x_b)
+			this->_bus->write(addr, this->_registers.yl);
+		else {
+			this->_bus->write(addr, this->_registers.yl);
+			this->_bus->write(addr + 1, this->_registers.yh);
+		}
+	}
+
+	void CPU::STZ(uint24_t addr)
+	{
+		this->_bus->write(addr, 0x00);
+		if (!this->_registers.p.m)
+			this->_bus->write(addr + 1, 0x00);
+	}
 }
\ No newline at end of file
diff --git a/tests/CPU/testStore.cpp b/tests/CPU/testStore.cpp
index 7610aac..fae97ba 100644
--- a/tests/CPU/testStore.cpp
+++ b/tests/CPU/testStore.cpp
@@ -47,4 +47,45 @@ Test(STX, 16bits)
 	pair.second.cpu->STX(0x0);
 	auto data = pair.second.wram->_data[0] + (pair.second.wram->_data[1] << 8u);
 	cr_assert_eq(data, 0x11AB, "The stored value should be 0x11AB but it was 0x%x.", data);
+}
+
+Test(STY, 8bits)
+{
+	auto pair = Init();
+	pair.second.cpu->_registers.p.x_b = true;
+	pair.second.cpu->_registers.y = 0x11;
+	pair.second.cpu->STY(0x0);
+	auto data = pair.second.wram->_data[0];
+	cr_assert_eq(data, 0x11, "The stored value should be 0x11 but it was 0x%x.", data);
+}
+
+Test(STY, 16bits)
+{
+	auto pair = Init();
+	pair.second.cpu->_registers.p.x_b = false;
+	pair.second.cpu->_registers.y = 0x11AB;
+	pair.second.cpu->STY(0x0);
+	auto data = pair.second.wram->_data[0] + (pair.second.wram->_data[1] << 8u);
+	cr_assert_eq(data, 0x11AB, "The stored value should be 0x11AB but it was 0x%x.", data);
+}
+
+Test(STZ, 8bits)
+{
+	auto pair = Init();
+	pair.second.cpu->_registers.p.m = true;
+	pair.second.wram->_data[0] = 0x11;
+	pair.second.cpu->STZ(0x0);
+	auto data = pair.second.wram->_data[0];
+	cr_assert_eq(data, 0x00, "The stored value should be 0x00 but it was 0x%x.", data);
+}
+
+Test(STZ, 16bits)
+{
+	auto pair = Init();
+	pair.second.cpu->_registers.p.m = false;
+	pair.second.wram->_data[0] = 0x11;
+	pair.second.wram->_data[1] = 0x11;
+	pair.second.cpu->STZ(0x0);
+	auto data = pair.second.wram->_data[0] + (pair.second.wram->_data[1] << 8u);
+	cr_assert_eq(data, 0x00, "The stored value should be 0x00 but it was 0x%x.", data);
 }
\ No newline at end of file