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Solving timing issues

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This commit is contained in:
Anonymus Raccoon
2020-03-28 20:47:13 +01:00
parent f44cd8a106
commit 9be49e283d
18 changed files with 432 additions and 485 deletions
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91
sources/CPU/Instructions/MemoryInstructions.cpp
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@@ -6,7 +6,7 @@
namespace ComSquare::CPU
{
int CPU::STA(uint24_t addr)
int CPU::STA(uint24_t addr, AddressingMode mode)
{
if (this->_registers.p.m)
this->_bus->write(addr, this->_registers.al);
@@ -14,10 +14,24 @@ namespace ComSquare::CPU
this->_bus->write(addr, this->_registers.al);
this->_bus->write(addr + 1, this->_registers.ah);
}
return 0;
int cycles = !this->_registers.p.m;
switch (mode) {
case DirectPage:
case DirectPageIndirect:
case DirectPageIndirectLong:
case DirectPageIndexedByX:
case DirectPageIndirectIndexedByX:
case DirectPageIndirectIndexedByY:
case DirectPageIndirectIndexedByYLong:
cycles += this->_registers.dl != 0;
default:
break;
}
return cycles;
}
int CPU::STX(uint24_t addr)
int CPU::STX(uint24_t addr, AddressingMode mode)
{
if (this->_registers.p.x_b)
this->_bus->write(addr, this->_registers.xl);
@@ -25,10 +39,10 @@ namespace ComSquare::CPU
this->_bus->write(addr, this->_registers.xl);
this->_bus->write(addr + 1, this->_registers.xh);
}
return 0;
return !this->_registers.p.x_b + (mode != Absolute && this->_registers.dl != 0);
}
int CPU::STY(uint24_t addr)
int CPU::STY(uint24_t addr, AddressingMode mode)
{
if (this->_registers.p.x_b)
this->_bus->write(addr, this->_registers.yl);
@@ -36,18 +50,20 @@ namespace ComSquare::CPU
this->_bus->write(addr, this->_registers.yl);
this->_bus->write(addr + 1, this->_registers.yh);
}
return 0;
return !this->_registers.p.x_b + (mode != Absolute && this->_registers.dl != 0);
}
int CPU::STZ(uint24_t addr)
int CPU::STZ(uint24_t addr, AddressingMode mode)
{
this->_bus->write(addr, 0x00);
if (!this->_registers.p.m)
this->_bus->write(addr + 1, 0x00);
return 0;
if (mode == Absolute || mode == AbsoluteIndexedByX)
return !this->_registers.p.m;
return !this->_registers.p.m + this->_registers.dl != 0;
}
int CPU::LDA(uint24_t addr)
int CPU::LDA(uint24_t addr, AddressingMode mode)
{
if (this->_registers.p.m) {
this->_registers.a = this->_bus->read(addr);
@@ -58,10 +74,31 @@ namespace ComSquare::CPU
this->_registers.p.n = this->_registers.a & 0xF000u;
}
this->_registers.p.z = this->_registers.a == 0x0;
return 0;
int cycles = !this->_registers.p.m;
switch (mode) {
case DirectPage:
case DirectPageIndirect:
case DirectPageIndirectLong:
case DirectPageIndexedByX:
case DirectPageIndirectIndexedByX:
case DirectPageIndirectIndexedByYLong:
cycles += this->_registers.dl != 0;
break;
case AbsoluteIndexedByX:
case AbsoluteIndexedByY:
cycles += this->_hasIndexCrossedPageBoundary;
break;
case DirectPageIndirectIndexedByY:
cycles += this->_registers.dl != 0 + this->_hasIndexCrossedPageBoundary;
break;
default:
break;
}
return cycles;
}
int CPU::LDX(uint24_t addr)
int CPU::LDX(uint24_t addr, AddressingMode mode)
{
if (this->_registers.p.x_b) {
this->_registers.x = this->_bus->read(addr);
@@ -72,10 +109,23 @@ namespace ComSquare::CPU
this->_registers.p.n = this->_registers.x & 0xF000u;
}
this->_registers.p.z = this->_registers.x == 0x0;
return 0;
int cycles = !this->_registers.p.x_b;
switch (mode) {
case DirectPage:
case DirectPageIndexedByY:
cycles += this->_registers.dl != 0;
break;
case AbsoluteIndexedByY:
cycles += this->_hasIndexCrossedPageBoundary;
break;
default:
break;
}
return cycles;
}
int CPU::LDY(uint24_t addr)
int CPU::LDY(uint24_t addr, AddressingMode mode)
{
if (this->_registers.p.x_b) {
this->_registers.y = this->_bus->read(addr);
@@ -86,6 +136,19 @@ namespace ComSquare::CPU
this->_registers.p.n = this->_registers.y & 0xF000u;
}
this->_registers.p.z = this->_registers.y == 0x0;
return 0;
int cycles = !this->_registers.p.x_b;
switch (mode) {
case DirectPage:
case DirectPageIndexedByY:
cycles += this->_registers.dl != 0;
break;
case AbsoluteIndexedByY:
cycles += this->_hasIndexCrossedPageBoundary;
break;
default:
break;
}
return cycles;
}
}