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Implementing TRB
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@@ -417,6 +417,8 @@ namespace ComSquare::CPU
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int TYX(uint24_t, AddressingMode);
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//! @brief Test and Set Memory Bits Against Accumulator
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int TSB(uint24_t, AddressingMode);
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//! @brief Test and Reset Memory Bits Against Accumulator
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int TRB(uint24_t, AddressingMode);
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//! @brief Exchange the B and A Accumulators
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int XBA(uint24_t, AddressingMode);
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//! @brief Test Memory Bits against Accumulator
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@@ -453,7 +455,7 @@ namespace ComSquare::CPU
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{&CPU::ORA, 5, "ora", AddressingMode::DirectPageIndirectIndexedByY, 2}, // 11
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{&CPU::ORA, 5, "ora", AddressingMode::DirectPageIndirect, 2}, // 12
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{&CPU::ORA, 7, "ora", AddressingMode::StackRelativeIndirectIndexedByY, 2}, // 13
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{&CPU::BRK, 7, "trb #-#", AddressingMode::Implied, 2}, // 14
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{&CPU::TRB, 5, "trb", AddressingMode::DirectPage, 2}, // 14
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{&CPU::ORA, 4, "ora", AddressingMode::DirectPageIndexedByX, 2}, // 15
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{&CPU::ASL, 6, "asl", AddressingMode::DirectPageIndexedByX, 2}, // 16
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{&CPU::ORA, 6, "ora", AddressingMode::DirectPageIndirectIndexedByYLong, 2}, // 17
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@@ -461,7 +463,7 @@ namespace ComSquare::CPU
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{&CPU::ORA, 4, "ora", AddressingMode::AbsoluteIndexedByY, 3}, // 19
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{&CPU::INC, 2, "inc", AddressingMode::Implied, 1}, // 1A
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{&CPU::TCS, 2, "tcs", AddressingMode::Implied, 1}, // 1B
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{&CPU::BRK, 7, "trb #-#", AddressingMode::Implied, 2}, // 1C
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{&CPU::TRB, 6, "trb", AddressingMode::Absolute, 3}, // 1C
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{&CPU::ORA, 4, "ora", AddressingMode::AbsoluteIndexedByX, 3}, // 1D
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{&CPU::ASL, 7, "asl", AddressingMode::AbsoluteIndexedByX, 3}, // 1E
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{&CPU::ORA, 5, "ora", AddressingMode::AbsoluteIndexedByXLong, 4}, // 1F
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@@ -28,6 +28,27 @@ namespace ComSquare::CPU
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return cycles;
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}
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int CPU::TRB(uint24_t valueAddr, AddressingMode mode)
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{
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uint16_t value = this->_bus->read(valueAddr);
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if (!this->_registers.p.m)
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value += this->_bus->read(valueAddr + 1) << 8u;
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uint16_t newValue = value & ~this->_registers.a;
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this->_bus->write(valueAddr, newValue);
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if (!this->_registers.p.m)
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this->_bus->write(valueAddr + 1, newValue >> 8u);
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this->_registers.p.z = (value & this->_registers.a) == 0;
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int cycles = 0;
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if (!this->_registers.p.m)
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cycles += 2;
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if (mode == DirectPage)
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cycles += this->_registers.dl != 0;
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return cycles;
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}
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int CPU::BIT(uint24_t valueAddr, AddressingMode mode)
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{
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unsigned negativeMask = this->_registers.p.m ? 0x80u : 0x8000u;
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@@ -297,4 +297,39 @@ Test(ROR, accumulator)
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cr_assert_eq(snes.cpu->_registers.p.z, false, "The zero flag should not be set.");
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cr_assert_eq(snes.cpu->_registers.p.c, true, "The carry flag should be set.");
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cr_assert_eq(snes.cpu->_registers.p.n, false, "The negative flag should not be set.");
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}
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Test(TRB, emulationTest)
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{
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Init()
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snes.wram->_data[0] = 0xFF;
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snes.cpu->_registers.a = 0b00110111;
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snes.cpu->_registers.p.m = true;
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snes.cpu->TRB(0x0, ComSquare::CPU::AddressingMode::Implied);
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cr_assert_eq(snes.wram->_data[0], 0b11001000, "The data in ram should be 0b11001000 but it was %x", snes.wram->_data[0]);
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cr_assert_eq(snes.cpu->_registers.p.z, false, "The zero flag should not be set.");
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}
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Test(TRB, nativeTest)
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{
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Init()
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snes.wram->_data[0] = 0xF0;
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snes.wram->_data[1] = 0x0F;
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snes.cpu->_registers.a = 0x0F0F;
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snes.cpu->_registers.p.m = false;
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snes.cpu->TRB(0x0, ComSquare::CPU::AddressingMode::Implied);
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cr_assert_eq(snes.wram->_data[0], 0xF0, "The first data in ram should be 0xF0 but it was %x", snes.wram->_data[0]);
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cr_assert_eq(snes.wram->_data[1], 0x00, "The second data in ram should be 0x00 but it was %x", snes.wram->_data[1]);
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cr_assert_eq(snes.cpu->_registers.p.z, false, "The zero flag should not be set.");
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}
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Test(TRB, zero)
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{
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Init()
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snes.wram->_data[0] = 0xFF;
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snes.cpu->_registers.a = 0b0;
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snes.cpu->_registers.p.m = true;
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snes.cpu->TRB(0x0, ComSquare::CPU::AddressingMode::Implied);
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cr_assert_eq(snes.wram->_data[0], 0xFF, "The data in ram should be 0xFF but it was %x", snes.wram->_data[0]);
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cr_assert_eq(snes.cpu->_registers.p.z, true, "The zero flag should be set.");
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}
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