mirror of
https://github.com/zoriya/ComSquare.git
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Fixing space indent to tab
This commit is contained in:
Melefo
+256
-256
@@ -48,262 +48,262 @@ namespace ComSquare::Debugger
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private:
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private:
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//! @brief List of instructions and their information
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//! @brief List of instructions and their information
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std::array<Instruction, 0x100> _instructions {{
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std::array<Instruction, 0x100> _instructions {{
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{"NOP", 1, {None, None}},
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{"NOP", 1, {None, None}},
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{"TCALL", 1, {None, None}},
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{"TCALL", 1, {None, None}},
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{"SET1", 2, {DirectAddr, None}},
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{"SET1", 2, {DirectAddr, None}},
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{"BBS", 3, {DirectAddr, ImmediateData}},
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{"BBS", 3, {DirectAddr, ImmediateData}},
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{"OR", 2, {DirectAddr, None}},
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{"OR", 2, {DirectAddr, None}},
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{"OR", 3, {AbsoluteAddr, None}},
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{"OR", 3, {AbsoluteAddr, None}},
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{"OR", 1, {IndexXAddr, None}},
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{"OR", 1, {IndexXAddr, None}},
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{"OR", 2, {AbsoluteDirectByXAddr, None}},
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{"OR", 2, {AbsoluteDirectByXAddr, None}},
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{"OR", 2, {ImmediateData, None}},
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{"OR", 2, {ImmediateData, None}},
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{"OR", 3, {DirectAddr, DirectAddr}},
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{"OR", 3, {DirectAddr, DirectAddr}},
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{"OR1", 3, {AbsoluteBit, None}},
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{"OR1", 3, {AbsoluteBit, None}},
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{"ASL", 2, {DirectAddr, None}},
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{"ASL", 2, {DirectAddr, None}},
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{"ASL", 3, {AbsoluteAddr, None}},
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{"ASL", 3, {AbsoluteAddr, None}},
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{"PUSH", 1, {PSW, None}},
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{"PUSH", 1, {PSW, None}},
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{"TSET1", 3, {AbsoluteAddr, None}},
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{"TSET1", 3, {AbsoluteAddr, None}},
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{"BRK", 1, {None, None}},
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{"BRK", 1, {None, None}},
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{"BPL", 2, {ImmediateData, None}},
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{"BPL", 2, {ImmediateData, None}},
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{"TCALL", 1, {None, None}},
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{"TCALL", 1, {None, None}},
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{"CLR1", 2, {DirectAddr, None}},
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{"CLR1", 2, {DirectAddr, None}},
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{"BBC", 3, {DirectAddr, ImmediateData}},
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{"BBC", 3, {DirectAddr, ImmediateData}},
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{"OR", 2, {DirectAddrByX, None}},
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{"OR", 2, {DirectAddrByX, None}},
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{"OR", 3, {AbsoluteAddrByX, None}},
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{"OR", 3, {AbsoluteAddrByX, None}},
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{"OR", 3, {AbsoluteAddrByY, None}},
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{"OR", 3, {AbsoluteAddrByY, None}},
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{"OR", 2, {AbsoluteDirectAddrByY, None}},
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{"OR", 2, {AbsoluteDirectAddrByY, None}},
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{"OR", 3, {DirectAddr, ImmediateData}},
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{"OR", 3, {DirectAddr, ImmediateData}},
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{"OR", 1, {IndexYAddr, IndexYAddr}},
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{"OR", 1, {IndexYAddr, IndexYAddr}},
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{"DECW", 2, {DirectAddr, None}},
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{"DECW", 2, {DirectAddr, None}},
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{"ASL", 2, {DirectAddrByX, None}},
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{"ASL", 2, {DirectAddrByX, None}},
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{"ASL", 1, {A, None}},
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{"ASL", 1, {A, None}},
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{"DEC", 1, {X, None}},
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{"DEC", 1, {X, None}},
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{"CMP", 3, {X, AbsoluteAddr}},
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{"CMP", 3, {X, AbsoluteAddr}},
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{"JMP", 3, {AbsoluteByXAddr, None}},
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{"JMP", 3, {AbsoluteByXAddr, None}},
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{"CLRP", 1, {None, None}},
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{"CLRP", 1, {None, None}},
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{"TCALL", 1, {None, None}},
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{"TCALL", 1, {None, None}},
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{"SET1", 2, {DirectAddr, None}},
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{"SET1", 2, {DirectAddr, None}},
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{"BBS", 3, {DirectAddr, ImmediateData}},
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{"BBS", 3, {DirectAddr, ImmediateData}},
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{"AND", 2, {DirectAddr, None}},
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{"AND", 2, {DirectAddr, None}},
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{"AND", 3, {AbsoluteAddr, None}},
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{"AND", 3, {AbsoluteAddr, None}},
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{"AND", 1, {IndexXAddr, None}},
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{"AND", 1, {IndexXAddr, None}},
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{"AND", 2, {AbsoluteDirectByXAddr, None}},
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{"AND", 2, {AbsoluteDirectByXAddr, None}},
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{"AND", 2, {ImmediateData, None}},
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{"AND", 2, {ImmediateData, None}},
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{"AND", 3, {DirectAddr, DirectAddr}},
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{"AND", 3, {DirectAddr, DirectAddr}},
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{"OR1", 3, {AbsoluteBit, None}},
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{"OR1", 3, {AbsoluteBit, None}},
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{"ROL", 2, {DirectAddr, None}},
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{"ROL", 2, {DirectAddr, None}},
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{"ROL", 3, {AbsoluteAddr, None}},
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{"ROL", 3, {AbsoluteAddr, None}},
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{"PUSH", 1, {A, None}},
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{"PUSH", 1, {A, None}},
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{"CBNE", 3, {DirectAddrByX, ImmediateData}},
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{"CBNE", 3, {DirectAddrByX, ImmediateData}},
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{"BRA", 2, {ImmediateData, None}},
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{"BRA", 2, {ImmediateData, None}},
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{"BMI", 2, {ImmediateData, None}},
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{"BMI", 2, {ImmediateData, None}},
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{"TCALL", 1, {None, None}},
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{"TCALL", 1, {None, None}},
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{"CLR1", 2, {DirectAddr, None}},
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{"CLR1", 2, {DirectAddr, None}},
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{"BBC", 3, {DirectAddr, ImmediateData}},
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{"BBC", 3, {DirectAddr, ImmediateData}},
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{"AND", 2, {DirectAddrByX, None}},
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{"AND", 2, {DirectAddrByX, None}},
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{"AND", 3, {AbsoluteAddrByX, None}},
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{"AND", 3, {AbsoluteAddrByX, None}},
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{"AND", 3, {AbsoluteAddrByY, None}},
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{"AND", 3, {AbsoluteAddrByY, None}},
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{"AND", 2, {AbsoluteDirectAddrByY, None}},
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{"AND", 2, {AbsoluteDirectAddrByY, None}},
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{"AND", 3, {DirectAddr, ImmediateData}},
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{"AND", 3, {DirectAddr, ImmediateData}},
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{"AND", 1, {IndexXAddr, IndexYAddr}},
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{"AND", 1, {IndexXAddr, IndexYAddr}},
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{"INCW", 2, {DirectAddr, None}},
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{"INCW", 2, {DirectAddr, None}},
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{"ROL", 2, {AbsoluteAddrByX, None}},
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{"ROL", 2, {AbsoluteAddrByX, None}},
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{"ROL", 1, {A, None}},
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{"ROL", 1, {A, None}},
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{"INC", 1, {X, None}},
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{"INC", 1, {X, None}},
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{"CMP", 2, {X, DirectAddr}},
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{"CMP", 2, {X, DirectAddr}},
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{"CALL", 3, {AbsoluteAddr, None}},
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{"CALL", 3, {AbsoluteAddr, None}},
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{"SETP", 1, {None, None}},
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{"SETP", 1, {None, None}},
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{"TCALL", 1, {None, None}},
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{"TCALL", 1, {None, None}},
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{"SET1", 2, {DirectAddr, None}},
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{"SET1", 2, {DirectAddr, None}},
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{"BBS", 3, {DirectAddr, ImmediateData}},
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{"BBS", 3, {DirectAddr, ImmediateData}},
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{"EOR", 2, {DirectAddr, None}},
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{"EOR", 2, {DirectAddr, None}},
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{"EOR", 3, {AbsoluteAddr, None}},
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{"EOR", 3, {AbsoluteAddr, None}},
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{"EOR", 1, {IndexXAddr, None}},
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{"EOR", 1, {IndexXAddr, None}},
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{"EOR", 2, {AbsoluteDirectByXAddr, None}},
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{"EOR", 2, {AbsoluteDirectByXAddr, None}},
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{"EOR", 2, {ImmediateData, None}},
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{"EOR", 2, {ImmediateData, None}},
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{"EOR", 3, {DirectAddr, DirectAddr}},
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{"EOR", 3, {DirectAddr, DirectAddr}},
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{"AND1", 3, {AbsoluteBit, None}},
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{"AND1", 3, {AbsoluteBit, None}},
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{"LSR", 2, {DirectAddr, None}},
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{"LSR", 2, {DirectAddr, None}},
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{"LSR", 3, {AbsoluteAddr, None}},
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{"LSR", 3, {AbsoluteAddr, None}},
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{"PUSH", 1, {X, None}},
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{"PUSH", 1, {X, None}},
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{"TCLR1", 3, {AbsoluteAddr, None}},
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{"TCLR1", 3, {AbsoluteAddr, None}},
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{"PCALL", 3, {None, None}},
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{"PCALL", 3, {None, None}},
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{"BVC", 2, {ImmediateData, None}},
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{"BVC", 2, {ImmediateData, None}},
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{"TCALL", 1, {None, None}},
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{"TCALL", 1, {None, None}},
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{"CLR1", 2, {DirectAddr, None}},
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{"CLR1", 2, {DirectAddr, None}},
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{"BBC", 3, {DirectAddr, ImmediateData}},
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{"BBC", 3, {DirectAddr, ImmediateData}},
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{"EOR", 2, {DirectAddrByX, None}},
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{"EOR", 2, {DirectAddrByX, None}},
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{"EOR", 3, {AbsoluteAddrByX, None}},
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{"EOR", 3, {AbsoluteAddrByX, None}},
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{"EOR", 3, {AbsoluteAddrByY, None}},
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{"EOR", 3, {AbsoluteAddrByY, None}},
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{"EOR", 2, {AbsoluteDirectAddrByY, None}},
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{"EOR", 2, {AbsoluteDirectAddrByY, None}},
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{"EOR", 3, {DirectAddr, ImmediateData}},
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{"EOR", 3, {DirectAddr, ImmediateData}},
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{"EOR", 1, {IndexXAddr, IndexYAddr}},
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{"EOR", 1, {IndexXAddr, IndexYAddr}},
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{"CMPW", 2, {DirectAddr, None}},
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{"CMPW", 2, {DirectAddr, None}},
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{"LSR", 2, {DirectAddrByX, None}},
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{"LSR", 2, {DirectAddrByX, None}},
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{"LSR", 1, {A, None}},
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{"LSR", 1, {A, None}},
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{"MOV", 1, {A, X}},
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{"MOV", 1, {A, X}},
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{"CMP", 3, {Y, AbsoluteAddr}},
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{"CMP", 3, {Y, AbsoluteAddr}},
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{"JMP", 3, {AbsoluteAddr, None}},
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{"JMP", 3, {AbsoluteAddr, None}},
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{"CLRC", 1, {None, None}},
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{"CLRC", 1, {None, None}},
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{"TCALL", 1, {None, None}},
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{"TCALL", 1, {None, None}},
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{"SET1", 2, {DirectAddr, None}},
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{"SET1", 2, {DirectAddr, None}},
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{"BBS", 3, {DirectAddr, ImmediateData}},
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{"BBS", 3, {DirectAddr, ImmediateData}},
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{"CMP", 2, {A, DirectAddr}},
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{"CMP", 2, {A, DirectAddr}},
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{"CMP", 3, {A, AbsoluteAddr}},
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{"CMP", 3, {A, AbsoluteAddr}},
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{"CMP", 1, {A, IndexXAddr,}},
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{"CMP", 1, {A, IndexXAddr,}},
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{"CMP", 2, {A, AbsoluteDirectByXAddr}},
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{"CMP", 2, {A, AbsoluteDirectByXAddr}},
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{"CMP", 2, {A, ImmediateData}},
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{"CMP", 2, {A, ImmediateData}},
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{"CMP", 3, {DirectAddr, DirectAddr}},
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{"CMP", 3, {DirectAddr, DirectAddr}},
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{"AND1", 3, {AbsoluteBit, None}},
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{"AND1", 3, {AbsoluteBit, None}},
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{"ROR", 2, {DirectAddr , None}},
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{"ROR", 2, {DirectAddr , None}},
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{"ROR", 3, {AbsoluteAddr, None}},
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{"ROR", 3, {AbsoluteAddr, None}},
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{"PUSH", 1, {Y, None}},
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{"PUSH", 1, {Y, None}},
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{"DBNZ", 3, {ImmediateData, None}},
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{"DBNZ", 3, {ImmediateData, None}},
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{"RET", 1, {None, None}},
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{"RET", 1, {None, None}},
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{"BVS", 2, {ImmediateData, None}},
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{"BVS", 2, {ImmediateData, None}},
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{"TCALL", 1, {None, None}},
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{"TCALL", 1, {None, None}},
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{"CLR1", 2, {DirectAddr, None}},
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{"CLR1", 2, {DirectAddr, None}},
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{"BBC", 3, {DirectAddr, ImmediateData}},
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{"BBC", 3, {DirectAddr, ImmediateData}},
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{"CMP", 2, {A, DirectAddrByX}},
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{"CMP", 2, {A, DirectAddrByX}},
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{"CMP", 3, {A, AbsoluteAddrByX}},
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{"CMP", 3, {A, AbsoluteAddrByX}},
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{"CMP", 3, {A, AbsoluteAddrByY}},
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{"CMP", 3, {A, AbsoluteAddrByY}},
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{"CMP", 2, {A, AbsoluteDirectAddrByY}},
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{"CMP", 2, {A, AbsoluteDirectAddrByY}},
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{"CMP", 3, {DirectAddr, ImmediateData}},
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{"CMP", 3, {DirectAddr, ImmediateData}},
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{"CMP", 1, {IndexXAddr, IndexYAddr}},
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{"CMP", 1, {IndexXAddr, IndexYAddr}},
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{"ADDW", 2, {DirectAddr, None}},
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{"ADDW", 2, {DirectAddr, None}},
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{"ROR", 2, {DirectAddrByX, None}},
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{"ROR", 2, {DirectAddrByX, None}},
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{"ROR", 1, {A, None}},
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{"ROR", 1, {A, None}},
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{"MOV", 1, {X, A}},
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{"MOV", 1, {X, A}},
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{"CMP", 3, {Y, DirectAddr}},
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{"CMP", 3, {Y, DirectAddr}},
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{"RETI", 1, {None, None}},
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{"RETI", 1, {None, None}},
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{"SETC", 1, {None, None}},
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{"SETC", 1, {None, None}},
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{"TCALL", 1, {None, None}},
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{"TCALL", 1, {None, None}},
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{"SET1", 2, {DirectAddr, None}},
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{"SET1", 2, {DirectAddr, None}},
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{"BBS", 3, {DirectAddr, ImmediateData}},
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{"BBS", 3, {DirectAddr, ImmediateData}},
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{"ADC", 2, {DirectAddr, None}},
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{"ADC", 2, {DirectAddr, None}},
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{"ADC", 3, {AbsoluteAddr, None}},
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{"ADC", 3, {AbsoluteAddr, None}},
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{"ADC", 1, {IndexXAddr, None}},
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{"ADC", 1, {IndexXAddr, None}},
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{"ADC", 2, {AbsoluteDirectByXAddr, None}},
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{"ADC", 2, {AbsoluteDirectByXAddr, None}},
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{"ADC", 2, {ImmediateData, None}},
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{"ADC", 2, {ImmediateData, None}},
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{"ADC", 3, {DirectAddr, DirectAddr}},
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{"ADC", 3, {DirectAddr, DirectAddr}},
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{"EOR1", 3, {AbsoluteBit, None}},
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{"EOR1", 3, {AbsoluteBit, None}},
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{"DEC", 2, {DirectAddr, None}},
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{"DEC", 2, {DirectAddr, None}},
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{"DEC", 3, {AbsoluteAddr, None}},
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{"DEC", 3, {AbsoluteAddr, None}},
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{"MOV", 2, {ImmediateData, Y}},
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{"MOV", 2, {ImmediateData, Y}},
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{"POP", 1, {PSW, None}},
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{"POP", 1, {PSW, None}},
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{"MOV", 3, {DirectAddr, ImmediateData}},
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{"MOV", 3, {DirectAddr, ImmediateData}},
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{"BCC", 2, {ImmediateData, None}},
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{"BCC", 2, {ImmediateData, None}},
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{"TCALL", 1, {None, None}},
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{"TCALL", 1, {None, None}},
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{"CLR1", 2, {DirectAddr, None}},
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{"CLR1", 2, {DirectAddr, None}},
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{"BBC", 3, {DirectAddr, ImmediateData}},
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{"BBC", 3, {DirectAddr, ImmediateData}},
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{"ADC", 2, {DirectAddrByX, None}},
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{"ADC", 2, {DirectAddrByX, None}},
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{"ADC", 3, {AbsoluteAddrByX, None}},
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{"ADC", 3, {AbsoluteAddrByX, None}},
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{"ADC", 3, {AbsoluteAddrByY, None}},
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{"ADC", 3, {AbsoluteAddrByY, None}},
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{"ADC", 2, {AbsoluteDirectAddrByY, None}},
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{"ADC", 2, {AbsoluteDirectAddrByY, None}},
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{"ADC", 3, {DirectAddr, ImmediateData}},
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{"ADC", 3, {DirectAddr, ImmediateData}},
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{"ADC", 1, {IndexXAddr, IndexYAddr}},
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{"ADC", 1, {IndexXAddr, IndexYAddr}},
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{"SUBW", 2, {DirectAddr, None}},
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{"SUBW", 2, {DirectAddr, None}},
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{"DEC", 2, {DirectAddrByX, None}},
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{"DEC", 2, {DirectAddrByX, None}},
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{"DEC", 1, {A, None}},
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{"DEC", 1, {A, None}},
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{"MOV", 1, {SP, X}},
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{"MOV", 1, {SP, X}},
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{"DIV", 1, {None, None}},
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{"DIV", 1, {None, None}},
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{"XCN", 1, {None, None}},
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{"XCN", 1, {None, None}},
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{"EI", 1, {None, None}},
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{"EI", 1, {None, None}},
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{"TCALL", 1, {None, None}},
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{"TCALL", 1, {None, None}},
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{"SET1", 2, {DirectAddr, None}},
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{"SET1", 2, {DirectAddr, None}},
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{"BBS", 3, {DirectAddr, ImmediateData}},
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{"BBS", 3, {DirectAddr, ImmediateData}},
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{"SBC", 2, {DirectAddr, None}},
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{"SBC", 2, {DirectAddr, None}},
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{"SBC", 3, {AbsoluteAddr, None}},
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{"SBC", 3, {AbsoluteAddr, None}},
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{"SBC", 1, {IndexXAddr, None}},
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{"SBC", 1, {IndexXAddr, None}},
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{"SBC", 2, {AbsoluteDirectByXAddr, None}},
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{"SBC", 2, {AbsoluteDirectByXAddr, None}},
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{"SBC", 2, {ImmediateData, None}},
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{"SBC", 2, {ImmediateData, None}},
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{"SBC", 3, {DirectAddr, DirectAddr}},
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{"SBC", 3, {DirectAddr, DirectAddr}},
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{"MOV1", 3, {AbsoluteBit, None}},
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{"MOV1", 3, {AbsoluteBit, None}},
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{"INC", 2, {DirectAddr, None}},
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{"INC", 2, {DirectAddr, None}},
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{"INC", 3, {AbsoluteAddr, None}},
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{"INC", 3, {AbsoluteAddr, None}},
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{"CMP", 2, {Y, ImmediateData}},
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{"CMP", 2, {Y, ImmediateData}},
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{"POP", 1, {A, None}},
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{"POP", 1, {A, None}},
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{"MOV", 1, {A, IndexXAddr}},
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{"MOV", 1, {A, IndexXAddr}},
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{"BCS", 2, {ImmediateData, None}},
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{"BCS", 2, {ImmediateData, None}},
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{"TCALL", 1, {None, None}},
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{"TCALL", 1, {None, None}},
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{"CLR1", 2, {DirectAddr, None}},
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{"CLR1", 2, {DirectAddr, None}},
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{"BBC", 3, {DirectAddr, ImmediateData}},
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{"BBC", 3, {DirectAddr, ImmediateData}},
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{"SBC", 2, {DirectAddrByX, None}},
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{"SBC", 2, {DirectAddrByX, None}},
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{"SBC", 3, {AbsoluteAddrByX, None}},
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{"SBC", 3, {AbsoluteAddrByX, None}},
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{"SBC", 3, {AbsoluteAddrByY, None}},
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{"SBC", 3, {AbsoluteAddrByY, None}},
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{"SBC", 2, {AbsoluteDirectAddrByY, None}},
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{"SBC", 2, {AbsoluteDirectAddrByY, None}},
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{"SBC", 2, {DirectAddr, ImmediateData}},
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{"SBC", 2, {DirectAddr, ImmediateData}},
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{"SBC", 1, {IndexXAddr, IndexYAddr}},
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{"SBC", 1, {IndexXAddr, IndexYAddr}},
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{"MOVW", 2, {DirectAddr, None}},
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{"MOVW", 2, {DirectAddr, None}},
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{"INC", 2, {DirectAddrByX, None}},
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{"INC", 2, {DirectAddrByX, None}},
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{"INC", 1, {A, None}},
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{"INC", 1, {A, None}},
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{"MOV", 1, {X, SP}},
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{"MOV", 1, {X, SP}},
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{"DAS", 1, {None, None}},
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{"DAS", 1, {None, None}},
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{"MOV", 1, {IndexXAddr, A}},
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{"MOV", 1, {IndexXAddr, A}},
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{"DI", 1, {None, None}},
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{"DI", 1, {None, None}},
|
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{"TCALL", 1, {None, None}},
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{"TCALL", 1, {None, None}},
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{"SET1", 2, {DirectAddr, None}},
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{"SET1", 2, {DirectAddr, None}},
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{"BBS", 3, {DirectAddr, ImmediateData}},
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{"BBS", 3, {DirectAddr, ImmediateData}},
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{"MOV", 2, {A, DirectAddr}},
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{"MOV", 2, {A, DirectAddr}},
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{"MOV", 3, {A, AbsoluteAddr}},
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{"MOV", 3, {A, AbsoluteAddr}},
|
||||||
{"MOV", 1, {A, IndexXAddr}},
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{"MOV", 1, {A, IndexXAddr}},
|
||||||
{"MOV", 2, {A, AbsoluteDirectByXAddr}},
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{"MOV", 2, {A, AbsoluteDirectByXAddr}},
|
||||||
{"CMP", 2, {X, ImmediateData}},
|
{"CMP", 2, {X, ImmediateData}},
|
||||||
{"MOV", 3, {X, AbsoluteAddr}},
|
{"MOV", 3, {X, AbsoluteAddr}},
|
||||||
{"MOV1", 3, {AbsoluteBit, None}},
|
{"MOV1", 3, {AbsoluteBit, None}},
|
||||||
{"MOV", 2, {Y, DirectAddr}},
|
{"MOV", 2, {Y, DirectAddr}},
|
||||||
{"MOV", 3, {Y, AbsoluteAddr}},
|
{"MOV", 3, {Y, AbsoluteAddr}},
|
||||||
{"MOV", 2, {ImmediateData, X}},
|
{"MOV", 2, {ImmediateData, X}},
|
||||||
{"POP", 1, {X, None}},
|
{"POP", 1, {X, None}},
|
||||||
{"MUL", 1, {None, None}},
|
{"MUL", 1, {None, None}},
|
||||||
{"BNE", 2, {ImmediateData, None}},
|
{"BNE", 2, {ImmediateData, None}},
|
||||||
{"TCALL", 1, {None, None}},
|
{"TCALL", 1, {None, None}},
|
||||||
{"CLR1", 2, {DirectAddr, None}},
|
{"CLR1", 2, {DirectAddr, None}},
|
||||||
{"BBC", 3, {DirectAddr, ImmediateData}},
|
{"BBC", 3, {DirectAddr, ImmediateData}},
|
||||||
{"MOV", 2, {A, DirectAddrByX}},
|
{"MOV", 2, {A, DirectAddrByX}},
|
||||||
{"MOV", 3, {A, AbsoluteAddrByX}},
|
{"MOV", 3, {A, AbsoluteAddrByX}},
|
||||||
{"MOV", 3, {A, AbsoluteAddrByY}},
|
{"MOV", 3, {A, AbsoluteAddrByY}},
|
||||||
{"MOV", 2, {A, AbsoluteDirectAddrByY}},
|
{"MOV", 2, {A, AbsoluteDirectAddrByY}},
|
||||||
{"MOV", 2, {X, DirectAddr}},
|
{"MOV", 2, {X, DirectAddr}},
|
||||||
{"MOV", 2, {X, DirectAddrByY}},
|
{"MOV", 2, {X, DirectAddrByY}},
|
||||||
{"MOVW", 2, {DirectAddr, None}},
|
{"MOVW", 2, {DirectAddr, None}},
|
||||||
{"MOV", 2, {Y, DirectAddrByX}},
|
{"MOV", 2, {Y, DirectAddrByX}},
|
||||||
{"DEC", 1, {Y, None}},
|
{"DEC", 1, {Y, None}},
|
||||||
{"MOV", 1, {Y, A}},
|
{"MOV", 1, {Y, A}},
|
||||||
{"CBNE", 3, {DirectAddrByX, ImmediateData}},
|
{"CBNE", 3, {DirectAddrByX, ImmediateData}},
|
||||||
{"DAA", 1, {None, None}},
|
{"DAA", 1, {None, None}},
|
||||||
{"CLRV", 1, {None, None}},
|
{"CLRV", 1, {None, None}},
|
||||||
{"TCALL", 1, {None, None}},
|
{"TCALL", 1, {None, None}},
|
||||||
{"SET1", 2, {DirectAddr, None}},
|
{"SET1", 2, {DirectAddr, None}},
|
||||||
{"BBS", 3, {DirectAddr, ImmediateData}},
|
{"BBS", 3, {DirectAddr, ImmediateData}},
|
||||||
{"MOV", 2, {DirectAddr, A}},
|
{"MOV", 2, {DirectAddr, A}},
|
||||||
{"MOV", 3, {AbsoluteAddrByX, A}},
|
{"MOV", 3, {AbsoluteAddrByX, A}},
|
||||||
{"MOV", 1, {IndexXAddr, A}},
|
{"MOV", 1, {IndexXAddr, A}},
|
||||||
{"MOV", 2, {AbsoluteDirectByXAddr, A}},
|
{"MOV", 2, {AbsoluteDirectByXAddr, A}},
|
||||||
{"MOV", 2, {ImmediateData, A}},
|
{"MOV", 2, {ImmediateData, A}},
|
||||||
{"MOV", 3, {AbsoluteAddr, X}},
|
{"MOV", 3, {AbsoluteAddr, X}},
|
||||||
{"NOT1", 3, {AbsoluteBit, None}},
|
{"NOT1", 3, {AbsoluteBit, None}},
|
||||||
{"MOV", 2, {DirectAddr, Y}},
|
{"MOV", 2, {DirectAddr, Y}},
|
||||||
{"MOV", 3, {AbsoluteAddr, Y}},
|
{"MOV", 3, {AbsoluteAddr, Y}},
|
||||||
{"NOTC", 1, {None, None}},
|
{"NOTC", 1, {None, None}},
|
||||||
{"POP", 1, {Y, None}},
|
{"POP", 1, {Y, None}},
|
||||||
{"SLEEP", 1, {None, None}},
|
{"SLEEP", 1, {None, None}},
|
||||||
{"BEQ", 2, {ImmediateData, None}},
|
{"BEQ", 2, {ImmediateData, None}},
|
||||||
{"TCALL", 1, {None, None}},
|
{"TCALL", 1, {None, None}},
|
||||||
{"CLR1", 2, {DirectAddr, None}},
|
{"CLR1", 2, {DirectAddr, None}},
|
||||||
{"BBC", 3, {DirectAddr, ImmediateData}},
|
{"BBC", 3, {DirectAddr, ImmediateData}},
|
||||||
{"MOV", 2, {DirectAddrByX, A}},
|
{"MOV", 2, {DirectAddrByX, A}},
|
||||||
{"MOV", 3, {AbsoluteAddrByX, A}},
|
{"MOV", 3, {AbsoluteAddrByX, A}},
|
||||||
{"MOV", 3, {AbsoluteAddrByY, A}},
|
{"MOV", 3, {AbsoluteAddrByY, A}},
|
||||||
{"MOV", 2, {AbsoluteDirectAddrByY, A}},
|
{"MOV", 2, {AbsoluteDirectAddrByY, A}},
|
||||||
{"MOV", 2, {DirectAddr, X}},
|
{"MOV", 2, {DirectAddr, X}},
|
||||||
{"MOV", 2, {DirectAddrByY, X}},
|
{"MOV", 2, {DirectAddrByY, X}},
|
||||||
{"MOV", 3, {DirectAddr, DirectAddr}},
|
{"MOV", 3, {DirectAddr, DirectAddr}},
|
||||||
{"MOV", 2, {DirectAddrByX, Y}},
|
{"MOV", 2, {DirectAddrByX, Y}},
|
||||||
{"INC", 1, {Y, None}},
|
{"INC", 1, {Y, None}},
|
||||||
{"MOV", 1, {A, Y}},
|
{"MOV", 1, {A, Y}},
|
||||||
{"DBNZ", 3, {ImmediateData, None}},
|
{"DBNZ", 3, {ImmediateData, None}},
|
||||||
{"STOP", 1, {None, None}}
|
{"STOP", 1, {None, None}}
|
||||||
}};
|
}};
|
||||||
|
|
||||||
//! @brief Position of the last instruction executed
|
//! @brief Position of the last instruction executed
|
||||||
|
|||||||
Reference in New Issue
Block a user