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Enabling the memory bus debugger

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This commit is contained in:
Zoe Roux
2021-07-05 00:23:48 +02:00
parent f16815c36f
commit cb6fb8a240
20 changed files with 475 additions and 418 deletions
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sources/CPU/DMA/DMA.cpp
+12 -7
View File
@@ -7,11 +7,16 @@
namespace ComSquare::CPU
{
DMA::DMA(Memory::MemoryBus &bus)
DMA::DMA(Memory::IMemoryBus &bus)
: _bus(bus),
enabled(false)
{}
void DMA::setBus(Memory::IMemoryBus &bus)
{
this->_bus = bus;
}
uint8_t DMA::read(uint8_t addr) const
{
switch (addr) {
@@ -68,22 +73,22 @@ namespace ComSquare::CPU
// Address $2180 refers to the WRam data register.
// Write to/Read from this port when the a address is on the vram cause different behaviors.
if (this->_port == 0x80) {
auto accessor = this->_bus.getAccessor(aAddress);
auto accessor = this->getBus().getAccessor(aAddress);
if (accessor && accessor->getComponent() == WRam) {
// WRAM->$2180 The write is not performed but the time is consumed anyway.
if (this->_controlRegister.direction == AtoB)
return 8;
// $2180->WRAM No read is performed (so only 4 master cycles are needed) but the value written is invalid.
this->_bus.write(aAddress, 0xFF);
this->getBus().write(aAddress, 0xFF);
return 4;
}
}
if (this->_controlRegister.direction == AtoB) {
uint8_t data = this->_bus.read(aAddress);
this->_bus.write(bAddress, data);
uint8_t data = this->getBus().read(aAddress);
this->getBus().write(bAddress, data);
} else {
uint8_t data = this->_bus.read(bAddress);
this->_bus.write(aAddress, data);
uint8_t data = this->getBus().read(bAddress);
this->getBus().write(aAddress, data);
}
return 8;
}
sources/CPU/DMA/DMA.hpp
+11 -2
View File
@@ -93,9 +93,18 @@ namespace ComSquare::CPU
} _count {};
//! @brief The memory bus to use for read/write.
Memory::MemoryBus &_bus;
Memory::IMemoryBus &_bus;
public:
//! @brief Get the memory bus used by this CPU.
[[nodiscard]] inline Memory::IMemoryBus &getBus()
{
return this->_bus;
}
//! @brief Set the memory bus used by this CPU
//! @param bus The bus to use.
void setBus(Memory::IMemoryBus &bus);
//! @brief Is this channel set to run?
bool enabled;
@@ -116,7 +125,7 @@ namespace ComSquare::CPU
//! @brief Create a DMA channel with a given bus
//! @param bus The memory bus to use.
explicit DMA(Memory::MemoryBus &bus);
explicit DMA(Memory::IMemoryBus &bus);
//! @brief A DMA is copy constructable.
DMA(const DMA &) = default;
//! @brief A DMA is not assignable