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Fixing bugs with the DMA

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This commit is contained in:
Zoe Roux
2021-02-01 19:21:18 +01:00
parent fdfa0fc0d6
commit ced42a3bf9
11 changed files with 141 additions and 74 deletions
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sources/CPU/DMA/DMA.cpp
+4 -5
View File
@@ -72,13 +72,13 @@ namespace ComSquare::CPU
if (this->_port == 0x80) {
auto accessor = this->_bus->getAccessor(aAddress);
if (accessor && accessor->getComponent() == WRam) {
if (this->_controlRegister.direction == AToB)
if (this->_controlRegister.direction == AtoB)
return 8;
this->_bus->write(aAddress, 0xFF);
return 4;
}
}
if (this->_controlRegister.direction == AToB) {
if (this->_controlRegister.direction == AtoB) {
uint8_t data = this->_bus->read(aAddress);
this->_bus->write(bAddress, data);
} else {
@@ -88,11 +88,10 @@ namespace ComSquare::CPU
return 8;
}
uint8_t DMA::run(unsigned int maxCycles)
unsigned DMA::run(unsigned int maxCycles)
{
unsigned cycles = 8;
int i = 0;
std::cout << "Starting a DMA transfer" << std::endl;
do {
cycles += this->_writeOneByte(this->_aAddress.raw, 0x2100 | (this->_port + this->_getModeOffset(i)));
@@ -100,7 +99,7 @@ namespace ComSquare::CPU
this->_aAddress.page += this->_controlRegister.increment ? -1 : 1;
this->_count.raw--;
i++;
} while (this->_count.raw > 0);
} while (this->_count.raw > 0 && this->enabled);
this->enabled = false;
return cycles;
}
sources/CPU/DMA/DMA.hpp
+24 -21
View File
@@ -9,31 +9,34 @@
#include <memory>
#include "../../Models/Int24.hpp"
#include "../../Memory/MemoryBus.hpp"
#include "../../Debugger/RegisterViewer.hpp"
#ifdef DEBUGGER_ENABLED
#include "../../Debugger/RegisterViewer.hpp"
#endif
namespace ComSquare::CPU
{
//! @brief The first three bytes of the DMA's control register. Used to tell how many bytes/registers there is.
enum DMAMode {
//! @brief 1 byte is transferred to 1 register (write once)
OneToOne = 0b000,
//! @brief 2 byte is transferred to 2 register (write once)
TwoToTwo = 0b001,
//! @brief 2 byte is transferred to 1 register (write twice)
TwoToOne = 0b010,
//! @brief 4 byte is transferred to 2 register (write twice)
FourToTwo = 0b011,
//! @brief 4 byte is transferred to 4 register (write once)
FourToFour = 0b100
};
enum Direction {
AToB,
BToA
};
//! @brief Class handling all DMA/HDMA transfers (Direct Memory Access or H-Blank Direct Memory Access)
class DMA {
public:
//! @brief The first three bytes of the DMA's control register. Used to tell how many bytes/registers there is.
enum DMAMode {
//! @brief 1 byte is transferred to 1 register (write once)
OneToOne = 0b000,
//! @brief 2 byte is transferred to 2 register (write once)
TwoToTwo = 0b001,
//! @brief 2 byte is transferred to 1 register (write twice)
TwoToOne = 0b010,
//! @brief 4 byte is transferred to 2 register (write twice)
FourToTwo = 0b011,
//! @brief 4 byte is transferred to 4 register (write once)
FourToFour = 0b100
};
enum Direction {
AtoB,
BtoA
};
private:
//! @brief Write one byte using the A address, the port and the _direction. Handle special cases where no write occurs.
//! @return The number of cycles used.
@@ -92,7 +95,7 @@ namespace ComSquare::CPU
//! @brief Run the DMA for x cycles
//! @param cycles The maximum number of cycles this DMA should run.
//! @return the number of cycles taken
uint8_t run(unsigned cycles);
unsigned run(unsigned cycles);
DMA() = default;
DMA(std::shared_ptr<Memory::MemoryBus> bus);