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Implementing MVN

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This commit is contained in:
Anonymus Raccoon
2020-05-13 23:12:31 +02:00
parent 7fe28a8bcc
commit d0e4caf12e
5 changed files with 53 additions and 4 deletions
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sources/CPU/CPU.hpp
+10 -3
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@@ -443,6 +443,13 @@ namespace ComSquare::CPU
int PEA(uint24_t, AddressingMode);
//! @brief Stop the processor
int STP(uint24_t, AddressingMode);
//! @brief WDM Reserved for Future Expansion (used as a code breakpoint)
int WDM(uint24_t, AddressingMode);
//! @brief Block Move Next. This instruction is special: it takes parameter in the registers
//! @param X_register Source address
//! @param Y_register Destination address
//! @param C_register (16 bits accumulator) Length -1
int MVN(uint24_t, AddressingMode);
//! @brief All the instructions of the CPU.
//! @info Instructions are indexed by their opcode
@@ -513,7 +520,7 @@ namespace ComSquare::CPU
{&CPU::AND, 5, "and", AddressingMode::AbsoluteIndexedByXLong, 4}, // 3F
{&CPU::RTI, 6, "rti", AddressingMode::Implied, 1}, // 40
{&CPU::EOR, 6, "eor", AddressingMode::DirectPageIndirectIndexedByX, 2}, // 41
{&CPU::BRK, 7, "wdm #-#", AddressingMode::Implied, 2}, // 42
{&CPU::WDM, 2, "wdm", AddressingMode::Immediate8bits, 2}, // 42
{&CPU::EOR, 4, "eor", AddressingMode::StackRelative, 2}, // 43
{&CPU::BRK, 7, "mvp #-#", AddressingMode::Implied, 2}, // 44
{&CPU::EOR, 3, "eor", AddressingMode::DirectPage, 2}, // 45
@@ -531,7 +538,7 @@ namespace ComSquare::CPU
{&CPU::EOR, 5, "eor", AddressingMode::DirectPageIndirectIndexedByY, 2}, // 51
{&CPU::EOR, 5, "eor", AddressingMode::DirectPageIndirect, 2}, // 52
{&CPU::EOR, 4, "eor", AddressingMode::StackRelativeIndirectIndexedByY, 2}, // 53
{&CPU::BRK, 7, "mvn #-#", AddressingMode::Implied, 2}, // 54
{&CPU::MVN, 0, "mvn", AddressingMode::Immediate16bits, 2}, // 54
{&CPU::EOR, 4, "eor", AddressingMode::DirectPageIndexedByX, 2}, // 55
{&CPU::LSR, 6, "lsr", AddressingMode::DirectPageIndexedByX, 2}, // 56
{&CPU::EOR, 6, "eor", AddressingMode::DirectPageIndirectIndexedByYLong, 2}, // 57
@@ -618,7 +625,7 @@ namespace ComSquare::CPU
{&CPU::TAY, 2, "tay", AddressingMode::Implied, 1}, // A8
{&CPU::LDA, 2, "lda", AddressingMode::ImmediateForA, 2}, // A9
{&CPU::TAX, 2, "tax", AddressingMode::Implied, 1}, // AA
{&CPU::BRK, 7, "plb #-#", AddressingMode::Implied, 2}, // AB
{&CPU::PLB, 4, "plb", AddressingMode::Implied, 1}, // AB
{&CPU::LDY, 4, "ldy", AddressingMode::Absolute, 4}, // AC
{&CPU::LDA, 4, "lda", AddressingMode::Absolute, 3}, // AD
{&CPU::LDX, 4, "ldx", AddressingMode::Absolute, 3}, // AE
sources/CPU/Instructions/InternalInstruction.cpp
+5
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@@ -326,4 +326,9 @@ namespace ComSquare::CPU
this->_isStopped = true;
return 0;
}
int CPU::WDM(uint24_t, AddressingMode)
{
return 0;
}
}
sources/CPU/Instructions/TransferRegisters.cpp
+18
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@@ -2,6 +2,7 @@
// Created by anonymus-raccoon on 2/28/20.
//
#include <iostream>
#include "../CPU.hpp"
namespace ComSquare::CPU
@@ -150,4 +151,21 @@ namespace ComSquare::CPU
this->_registers.p.z = this->_registers.y == 0;
return 0;
}
int CPU::MVN(uint24_t params, AddressingMode)
{
uint8_t srcBank = params;
uint8_t destBank = params >> 8u;
int length = this->_registers.a + 1;
this->_registers.dbr = destBank;
while (this->_registers.a != 0xFFFF) {
uint8_t data = this->_bus->read(srcBank << 24u | this->_registers.x);
this->_bus->write(destBank << 24u | this->_registers.y, data);
this->_registers.x++;
this->_registers.y++;
this->_registers.a--;
}
return 7 * length;
}
}