From 8aa138de854e29213355395d9b30ff95ed9d3f27 Mon Sep 17 00:00:00 2001 From: AnonymusRaccoon Date: Thu, 13 Feb 2020 11:23:36 +0100 Subject: [PATCH 1/7] Finishing the STA --- sources/CPU/CPU.hpp | 12 ++++++------ tests/CPU/testStore.cpp | 30 ++++++++++++++++++++---------- 2 files changed, 26 insertions(+), 16 deletions(-) diff --git a/sources/CPU/CPU.hpp b/sources/CPU/CPU.hpp index f74a8bf..6980eea 100644 --- a/sources/CPU/CPU.hpp +++ b/sources/CPU/CPU.hpp @@ -18,8 +18,8 @@ namespace ComSquare::CPU //! @brief The Accumulator union { struct { - uint8_t ah; uint8_t al; + uint8_t ah; }; uint16_t a; }; @@ -28,8 +28,8 @@ namespace ComSquare::CPU //! @brief The Direct Page register; union { struct { - uint8_t dh; uint8_t dl; + uint8_t dh; }; uint16_t d; }; @@ -40,8 +40,8 @@ namespace ComSquare::CPU //! @brief The Program Counter; union { struct { - uint8_t pch; uint8_t pcl; + uint8_t pch; }; uint16_t pc; }; @@ -52,24 +52,24 @@ namespace ComSquare::CPU //! @brief The Stack pointer union { struct { - uint8_t sh; uint8_t sl; + uint8_t sh; }; uint16_t s; }; //! @brief The X index register union { struct { - uint8_t xh; uint8_t xl; + uint8_t xh; }; uint16_t x; }; //! @brief The Y index register union { struct { - uint8_t yh; uint8_t yl; + uint8_t yh; }; uint16_t y; }; diff --git a/tests/CPU/testStore.cpp b/tests/CPU/testStore.cpp index 914ecfc..c344c78 100644 --- a/tests/CPU/testStore.cpp +++ b/tests/CPU/testStore.cpp @@ -8,13 +8,23 @@ #include "../tests.hpp" #include "../../sources/SNES.hpp" using namespace ComSquare; -// -//Test(STA, 8bits) -//{ -// auto pair = Init(); -// pair.second.cpu->_registers.p.m = false; -// pair.second.cpu->_registers.a = 0x11; -// pair.second.cpu->STA(0x0); -// auto data = pair.second.wram->_data[0]; -// cr_assert_eq(data, 0x11, "The stored value should be 0x11 but it was 0x%x.", data); -//} \ No newline at end of file + +Test(STA, 8bits) +{ + auto pair = Init(); + pair.second.cpu->_registers.p.m = true; + pair.second.cpu->_registers.a = 0x11; + pair.second.cpu->STA(0x0); + auto data = pair.second.wram->_data[0]; + cr_assert_eq(data, 0x11, "The stored value should be 0x11 but it was 0x%x.", data); +} + +Test(STA, 16bits) +{ + auto pair = Init(); + pair.second.cpu->_registers.p.m = false; + pair.second.cpu->_registers.a = 0x11AB; + pair.second.cpu->STA(0x0); + auto data = pair.second.wram->_data[0] + (pair.second.wram->_data[1] << 8u); + cr_assert_eq(data, 0x11AB, "The stored value should be 0x11AB but it was 0x%x.", data); +} \ No newline at end of file From 4d30a3562096e1b499b0be8fa5fbc38d29183bba Mon Sep 17 00:00:00 2001 From: AnonymusRaccoon Date: Thu, 13 Feb 2020 13:55:01 +0100 Subject: [PATCH 2/7] Changing timing management --- CMakeLists.txt | 4 +- sources/CPU/CPU.cpp | 104 +++++++----------- sources/CPU/CPU.hpp | 41 ++++--- sources/CPU/Instructions/Interrupts.cpp | 19 ++-- .../Instructions/MathematicalOperations.cpp | 3 +- .../CPU/Instructions/MemoryInstructions.cpp | 18 +++ tests/CPU/testInterupts.cpp | 4 +- 7 files changed, 101 insertions(+), 92 deletions(-) create mode 100644 sources/CPU/Instructions/MemoryInstructions.cpp diff --git a/CMakeLists.txt b/CMakeLists.txt index 6243844..d3937f0 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -58,6 +58,7 @@ add_executable(unit_tests tests/PPU/testPpuWrite.cpp tests/PPU/testPpuWriteFromVmain.cpp sources/CPU/Instructions/MathematicalOperations.cpp + sources/CPU/Instructions/MemoryInstructions.cpp tests/CPU/Math/testADC.cpp tests/CPU/testStore.cpp ) @@ -113,7 +114,8 @@ add_executable(ComSquare sources/CPU/Instructions/CommonInstructions.hpp sources/Exceptions/InvalidOpcode.hpp sources/CPU/Instructions/Interrupts.cpp - sources/CPU/Instructions/MathematicalOperations.cpp) + sources/CPU/Instructions/MathematicalOperations.cpp + sources/CPU/Instructions/MemoryInstructions.cpp) target_link_libraries(ComSquare sfml-graphics diff --git a/sources/CPU/CPU.cpp b/sources/CPU/CPU.cpp index 40246b7..54403c0 100644 --- a/sources/CPU/CPU.cpp +++ b/sources/CPU/CPU.cpp @@ -190,59 +190,74 @@ namespace ComSquare::CPU unsigned cycles = 0; for (int i = 0; i < 0xFF; i++) - cycles += this->executeInstruction(); + cycles += this->_executeInstruction(); return cycles; } - unsigned CPU::executeInstruction() + unsigned CPU::_executeInstruction() { uint8_t opcode = this->_bus->read(this->_registers.pc); - this->_extraMemoryCycles = 0; + this->_hasIndexCrossedPageBoundary = false; switch (opcode) { - case Instructions::BRK: return 7 + this->BRK(); + case Instructions::BRK: this->BRK(); return 7 + !this->_isEmulationMode; - case Instructions::RTI: return 6 + this->RTI(); + case Instructions::RTI: this->RTI(); return 6 + !this->_isEmulationMode; - case Instructions::ADC_IM: return 2 + this->ADC(this->_getImmediateAddr()); - case Instructions::ADC_ABS: return 4 + this->ADC(this->_getAbsoluteAddr()); - case Instructions::ADC_ABSl: return 5 + this->ADC(this->_getAbsoluteLongAddr()); - case Instructions::ADC_DP: return 3 + this->ADC(this->_getDirectAddr()); - case Instructions::ADC_DPi: return 5 + this->ADC(this->_getDirectIndirectAddr()); - case Instructions::ADC_DPil: return 6 + this->ADC(this->_getDirectIndirectLongAddr()); - case Instructions::ADC_ABSX: return 4 + this->ADC(this->_getAbsoluteIndexedByXAddr()); - case Instructions::ADC_ABSXl:return 5 + this->ADC(this->_getAbsoluteIndexedByXLongAddr()); - case Instructions::ADC_ABSY: return 4 + this->ADC(this->_getAbsoluteIndexedByYAddr()); - case Instructions::ADC_DPX: return 4 + this->ADC(this->_getDirectIndexedByXAddr()); - case Instructions::ADC_DPXi: return 6 + this->ADC(this->_getDirectIndirectIndexedXAddr()); - case Instructions::ADC_DPYi: return 5 + this->ADC(this->_getDirectIndirectIndexedYAddr()); - case Instructions::ADC_DPYil:return 6 + this->ADC(this->_getDirectIndirectIndexedYLongAddr()); - case Instructions::ADC_SR: return 4 + this->ADC(this->_getStackRelativeAddr()); - case Instructions::ADC_SRYi: return 7 + this->ADC(this->_getStackRelativeIndirectIndexedYAddr()); + case Instructions::ADC_IM: this->ADC(this->_getImmediateAddr()); return 2 + !this->_registers.p.m; + case Instructions::ADC_ABS: this->ADC(this->_getAbsoluteAddr()); return 4 + !this->_registers.p.m; + case Instructions::ADC_ABSl: this->ADC(this->_getAbsoluteLongAddr()); return 5 + !this->_registers.p.m; + case Instructions::ADC_DP: this->ADC(this->_getDirectAddr()); return 3 + !this->_registers.p.m + this->_registers.dl != 0; + case Instructions::ADC_DPi: this->ADC(this->_getDirectIndirectAddr()); return 5 + !this->_registers.p.m + this->_registers.dl != 0; + case Instructions::ADC_DPil: this->ADC(this->_getDirectIndirectLongAddr()); return 6 + !this->_registers.p.m + this->_registers.dl != 0; + case Instructions::ADC_ABSX: this->ADC(this->_getAbsoluteIndexedByXAddr()); return 4 + !this->_registers.p.m + this->_hasIndexCrossedPageBoundary; + case Instructions::ADC_ABSXl:this->ADC(this->_getAbsoluteIndexedByXLongAddr()); return 5 + !this->_registers.p.m; + case Instructions::ADC_ABSY: this->ADC(this->_getAbsoluteIndexedByYAddr()); return 4 + !this->_registers.p.m + this->_hasIndexCrossedPageBoundary; + case Instructions::ADC_DPX: this->ADC(this->_getDirectIndexedByXAddr()); return 4 + !this->_registers.p.m + this->_registers.dl != 0; + case Instructions::ADC_DPXi: this->ADC(this->_getDirectIndirectIndexedXAddr()); return 6 + !this->_registers.p.m + this->_registers.dl != 0; + case Instructions::ADC_DPYi: this->ADC(this->_getDirectIndirectIndexedYAddr()); return 5 + !this->_registers.p.m + this->_registers.dl != 0 + this->_hasIndexCrossedPageBoundary; + case Instructions::ADC_DPYil:this->ADC(this->_getDirectIndirectIndexedYLongAddr()); return 6 + !this->_registers.p.m + this->_registers.dl != 0; + case Instructions::ADC_SR: this->ADC(this->_getStackRelativeAddr()); return 4 + !this->_registers.p.m; + case Instructions::ADC_SRYi: this->ADC(this->_getStackRelativeIndirectIndexedYAddr()); return 7 + !this->_registers.p.m; + + case Instructions::STA_ABS: this->STA(this->_getAbsoluteAddr()); return 4 + !this->_registers.p.m; + case Instructions::STA_ABSl: this->STA(this->_getAbsoluteLongAddr()); return 5 + !this->_registers.p.m; + case Instructions::STA_DP: this->STA(this->_getDirectAddr()); return 3 + !this->_registers.p.m + this->_registers.dl != 0; + case Instructions::STA_DPi: this->STA(this->_getDirectIndirectAddr()); return 5 + !this->_registers.p.m + this->_registers.dl != 0; + case Instructions::STA_DPil: this->STA(this->_getDirectIndirectLongAddr()); return 6 + !this->_registers.p.m + this->_registers.dl != 0; + case Instructions::STA_ABSX: this->STA(this->_getAbsoluteIndexedByXAddr()); return 5 + !this->_registers.p.m; + case Instructions::STA_ABSXl:this->STA(this->_getAbsoluteIndexedByXLongAddr()); return 5 + !this->_registers.p.m; + case Instructions::STA_ABSY: this->STA(this->_getAbsoluteIndexedByYAddr()); return 5 + !this->_registers.p.m; + case Instructions::STA_DPX: this->STA(this->_getDirectIndexedByXAddr()); return 4 + !this->_registers.p.m + this->_registers.dl != 0; + case Instructions::STA_DPXi: this->STA(this->_getDirectIndirectIndexedXAddr()); return 6 + !this->_registers.p.m + this->_registers.dl != 0; + case Instructions::STA_DPYi: this->STA(this->_getDirectIndirectIndexedYAddr()); return 6 + !this->_registers.p.m + this->_registers.dl != 0; + case Instructions::STA_DPYil:this->STA(this->_getDirectIndirectIndexedYLongAddr()); return 6 + !this->_registers.p.m + this->_registers.dl != 0; + case Instructions::STA_SR: this->STA(this->_getStackRelativeAddr()); return 4 + !this->_registers.p.m; + case Instructions::STA_SRYi: this->STA(this->_getStackRelativeIndirectIndexedYAddr()); return 7 + !this->_registers.p.m; default: throw InvalidOpcode("CPU", opcode); } } - void CPU::push(uint8_t data) + void CPU::_push(uint8_t data) { this->_bus->write(this->_registers.s--, data); } - void CPU::push(uint16_t data) + void CPU::_push(uint16_t data) { this->_bus->write(this->_registers.s--, data); this->_bus->write(this->_registers.s--, data << 8u); } - uint8_t CPU::pop() + uint8_t CPU::_pop() { return this->_bus->read(this->_registers.s++); } - uint16_t CPU::pop16() + uint16_t CPU::_pop16() { return this->_bus->read(this->_registers.s++) + (this->_bus->read(this->_registers.s++) << 8u); } @@ -261,9 +276,6 @@ namespace ComSquare::CPU uint24_t CPU::_getDirectAddr() { - if (this->_registers.dl != 0) - this->_extraMemoryCycles++; - uint8_t addr = this->_bus->read(this->_registers.pac++); return this->_registers.d + addr; } @@ -286,23 +298,17 @@ namespace ComSquare::CPU uint24_t CPU::_getDirectIndirectIndexedYAddr() { - if (this->_registers.dl != 0) - this->_extraMemoryCycles++; - uint16_t dp = this->_bus->read(this->_registers.pac++) + this->_registers.d; uint24_t base = this->_bus->read(dp); base += this->_bus->read(dp + 1) << 8u; base += this->_registers.dbr << 16u; if ((base & 0xF0000000u) == (((base + this->_registers.y) & 0xF0000000u))) - this->_extraMemoryCycles++; + this->_hasIndexCrossedPageBoundary = true; return base + this->_registers.y; } uint24_t CPU::_getDirectIndirectIndexedYLongAddr() { - if (this->_registers.dl != 0) - this->_extraMemoryCycles++; - uint16_t dp = this->_bus->read(this->_registers.pac++) + this->_registers.d; uint24_t base = this->_bus->read(dp); base += this->_bus->read(dp + 1) << 8u; @@ -312,9 +318,6 @@ namespace ComSquare::CPU uint24_t CPU::_getDirectIndirectIndexedXAddr() { - if (this->_registers.dl != 0) - this->_extraMemoryCycles++; - uint16_t dp = this->_bus->read(this->_registers.pac++) + this->_registers.d; dp += this->_registers.x; uint24_t base = this->_bus->read(dp); @@ -325,9 +328,6 @@ namespace ComSquare::CPU uint24_t CPU::_getDirectIndexedByXAddr() { - if (this->_registers.dl != 0) - this->_extraMemoryCycles++; - uint16_t dp = this->_bus->read(this->_registers.pac++) + this->_registers.d; dp += this->_registers.x; return dp; @@ -335,9 +335,6 @@ namespace ComSquare::CPU uint24_t CPU::_getDirectIndexedByYAddr() { - if (this->_registers.dl != 0) - this->_extraMemoryCycles++; - uint16_t dp = this->_bus->read(this->_registers.pac++) + this->_registers.d; dp += this->_registers.y; return dp; @@ -349,7 +346,7 @@ namespace ComSquare::CPU abs += this->_bus->read(this->_registers.pac++) << 8u; uint24_t effective = abs + (this->_registers.dbr << 16u); if ((effective & 0xF0000000u) == (((effective + this->_registers.x) & 0xF0000000u))) - this->_extraMemoryCycles++; + this->_hasIndexCrossedPageBoundary = true; return effective + this->_registers.x; } @@ -359,7 +356,7 @@ namespace ComSquare::CPU abs += this->_bus->read(this->_registers.pac++) << 8u; uint24_t effective = abs + (this->_registers.dbr << 16u); if ((effective & 0xF0000000u) == (((effective + this->_registers.y) & 0xF0000000u))) - this->_extraMemoryCycles++; + this->_hasIndexCrossedPageBoundary = true; return effective + this->_registers.y; } @@ -408,9 +405,6 @@ namespace ComSquare::CPU uint24_t CPU::_getDirectIndirectAddr() { - if (this->_registers.dl != 0) - this->_extraMemoryCycles++; - uint16_t dp = this->_bus->read(this->_registers.pac++) + this->_registers.d; uint24_t effective = this->_bus->read(dp); effective += this->_bus->read(dp + 1) << 8u; @@ -420,9 +414,6 @@ namespace ComSquare::CPU uint24_t CPU::_getDirectIndirectLongAddr() { - if (this->_registers.dl != 0) - this->_extraMemoryCycles++; - uint16_t dp = this->_bus->read(this->_registers.pac++) + this->_registers.d; uint24_t effective = this->_bus->read(dp); effective += this->_bus->read(++dp) << 8u; @@ -441,15 +432,4 @@ namespace ComSquare::CPU base += this->_registers.dbr << 16u; return base + this->_registers.y; } - - unsigned CPU::STA(uint24_t addr) - { - if (this->_registers.p.m) - this->_bus->write(addr, this->_registers.al); - else { - this->_bus->write(addr, this->_registers.al); - this->_bus->write(addr + 1, this->_registers.ah); - } - return 0; - } } \ No newline at end of file diff --git a/sources/CPU/CPU.hpp b/sources/CPU/CPU.hpp index 6980eea..b8d46c9 100644 --- a/sources/CPU/CPU.hpp +++ b/sources/CPU/CPU.hpp @@ -180,7 +180,7 @@ namespace ComSquare::CPU uint8_t joy4h; }; - //! @brief All the instructions opcode of the main CPI. + //! @brief All the instructions opcode of the main CPU. //! @info The name of the instruction followed by their parameters (after an underscore) if any. //! @info Addr mode with an i at the end means indirect. //! @info Addr mode with an l at the end means long. @@ -204,6 +204,21 @@ namespace ComSquare::CPU ADC_ABSY = 0x79, ADC_ABSX = 0x7D, ADC_ABSXl = 0x7F, + + STA_ABS = 0x8D, + STA_ABSl = 0x8F, + STA_DP = 0x85, + STA_DPi = 0x92, + STA_DPil = 0x87, + STA_ABSX = 0x9D, + STA_ABSXl = 0x9F, + STA_ABSY = 0x99, + STA_DPX = 0x95, + STA_DPXi = 0x81, + STA_DPYi = 0x91, + STA_DPYil = 0x97, + STA_SR = 0x83, + STA_SRYi = 0x93 }; //! @brief The main CPU @@ -220,8 +235,8 @@ namespace ComSquare::CPU //! @brief The cartridge header (stored for interrupt vectors.. Cartridge::Header &_cartridgeHeader; - //! @brief An additional number of cycles that the current running instruction took to run. (Used for address modes that take longer to run than others). - unsigned _extraMemoryCycles = 0; + //! @brief True if an addressing mode with an iterator (x, y) has crossed the page. (Used because crossing the page boundary take one more cycle to run certain instructions). + bool _hasIndexCrossedPageBoundary = false; //! @brief Immediate address mode is specified with a value. (This functions returns the 24bit space address of the value). uint24_t _getImmediateAddr(); @@ -266,30 +281,30 @@ namespace ComSquare::CPU //! @brief Push 8 bits of data to the stack. - void push(uint8_t data); + void _push(uint8_t data); //! @brief Push 16 bits of data to the stack. - void push(uint16_t data); + void _push(uint16_t data); //! @brief Pop 8 bits of data from the stack. - uint8_t pop(); + uint8_t _pop(); //! @brief Pop 16 bits of data from the stack. - uint16_t pop16(); + uint16_t _pop16(); //! @brief Execute a single instruction. //! @return The number of CPU cycles that the instruction took. - unsigned executeInstruction(); + unsigned _executeInstruction(); //! @brief Reset interrupt - Called on boot and when the reset button is pressed. - unsigned RESB(); + void RESB(); //! @brief Break instruction - Causes a software break. The PC is loaded from a vector table. - unsigned BRK(); + void BRK(); //! @brief Return from Interrupt - Used to return from a interrupt handler. - unsigned RTI(); + void RTI(); //! @brief Add with carry - Adds operand to the Accumulator; adds an additional 1 if carry is set. //! @return The number of extra cycles that this operation took. - unsigned ADC(uint24_t valueAddr); + void ADC(uint24_t valueAddr); //! @brief Store the accumulator to memory. - unsigned STA(uint24_t addr); + void STA(uint24_t addr); public: explicit CPU(std::shared_ptr bus, Cartridge::Header &cartridgeHeader); //! @brief This function continue to execute the Cartridge code. diff --git a/sources/CPU/Instructions/Interrupts.cpp b/sources/CPU/Instructions/Interrupts.cpp index b175048..c439e9f 100644 --- a/sources/CPU/Instructions/Interrupts.cpp +++ b/sources/CPU/Instructions/Interrupts.cpp @@ -6,7 +6,7 @@ namespace ComSquare::CPU { - unsigned CPU::RESB() + void CPU::RESB() { this->_registers.p.i = true; this->_registers.p.d = false; @@ -18,10 +18,9 @@ namespace ComSquare::CPU this->_registers.d = 0x0000; this->_registers.sh = 0x01; // the low bit of the stack pointer is undefined on reset. this->_registers.pc = this->_cartridgeHeader.emulationInterrupts.reset; - return 0; } - unsigned CPU::BRK() + void CPU::BRK() { // TODO rework this. The PC should be pushed to the stack. // Info here: http://softpixel.com/~cwright/sianse/docs/65816NFO.HTM at BRK Software Break @@ -33,18 +32,14 @@ namespace ComSquare::CPU else this->_registers.pc = this->_cartridgeHeader.nativeInterrupts.brk; this->_registers.p.d = false; - return !this->_isEmulationMode; } - unsigned CPU::RTI() + void CPU::RTI() { - this->_registers.p.flags = this->pop(); - this->_registers.pc = this->pop16(); + this->_registers.p.flags = this->_pop(); + this->_registers.pc = this->_pop16(); - if (!this->_isEmulationMode) { - this->_registers.pbr = this->pop16(); - return 1; - } - return 0; + if (!this->_isEmulationMode) + this->_registers.pbr = this->_pop16(); } } \ No newline at end of file diff --git a/sources/CPU/Instructions/MathematicalOperations.cpp b/sources/CPU/Instructions/MathematicalOperations.cpp index 78a8dc1..37a38e6 100644 --- a/sources/CPU/Instructions/MathematicalOperations.cpp +++ b/sources/CPU/Instructions/MathematicalOperations.cpp @@ -7,7 +7,7 @@ namespace ComSquare::CPU { - unsigned CPU::ADC(uint24_t valueAddr) + void CPU::ADC(uint24_t valueAddr) { unsigned value = this->_bus->read(valueAddr) + this->_registers.p.c; if (this->_registers.p.m) @@ -25,6 +25,5 @@ namespace ComSquare::CPU this->_registers.a %= 0x100; this->_registers.p.z = this->_registers.a == 0; this->_registers.p.n = this->_registers.a & negativeMask; - return this->_extraMemoryCycles + !this->_registers.p.m; } } \ No newline at end of file diff --git a/sources/CPU/Instructions/MemoryInstructions.cpp b/sources/CPU/Instructions/MemoryInstructions.cpp new file mode 100644 index 0000000..56bba9a --- /dev/null +++ b/sources/CPU/Instructions/MemoryInstructions.cpp @@ -0,0 +1,18 @@ +// +// Created by anonymus-raccoon on 2/13/20. +// + +#include "../CPU.hpp" + +namespace ComSquare::CPU +{ + void CPU::STA(uint24_t addr) + { + if (this->_registers.p.m) + this->_bus->write(addr, this->_registers.al); + else { + this->_bus->write(addr, this->_registers.al); + this->_bus->write(addr + 1, this->_registers.ah); + } + } +} \ No newline at end of file diff --git a/tests/CPU/testInterupts.cpp b/tests/CPU/testInterupts.cpp index dd6339b..2856cb3 100644 --- a/tests/CPU/testInterupts.cpp +++ b/tests/CPU/testInterupts.cpp @@ -16,7 +16,7 @@ Test(CPU_emulated, BRK) pair.second.cartridge->header.emulationInterrupts.brk = 0x123u; pair.second.cpu->_registers.p.d = true; pair.second.cpu->_registers.pc = 0x156u; - cr_assert_eq(pair.second.cpu->BRK(), 0); + pair.second.cpu->BRK(); cr_assert_eq(pair.second.cpu->_registers.pc, 0x123u); cr_assert_eq(pair.second.cpu->_registers.p.i, 1, "pair.second.cpu->_registers.p.i mmust be equal to 1 but it was %d", pair.second.cpu->_registers.p.i); cr_assert_eq(pair.second.cpu->_registers.p.d, false); @@ -28,7 +28,7 @@ Test(CPU_native, BRK) pair.second.cpu->_isEmulationMode = false; pair.second.cartridge->header.nativeInterrupts.brk = 0x123u; pair.second.cpu->_registers.pc = 0x156u; - cr_assert_eq(pair.second.cpu->BRK(), 1); + pair.second.cpu->BRK(); cr_assert_eq(pair.second.cpu->_registers.pc, 0x123u); cr_assert_eq(pair.second.cpu->_registers.p.i, true); cr_assert_eq(pair.second.cpu->_registers.p.d, false); From 997bb4fa7c2396e4cd0d006f37a8d499eee0d463 Mon Sep 17 00:00:00 2001 From: AnonymusRaccoon Date: Thu, 13 Feb 2020 14:05:47 +0100 Subject: [PATCH 3/7] Implementing the STX --- sources/CPU/CPU.cpp | 4 ++++ sources/CPU/CPU.hpp | 8 +++++++- .../CPU/Instructions/MemoryInstructions.cpp | 10 ++++++++++ tests/CPU/testStore.cpp | 20 +++++++++++++++++++ 4 files changed, 41 insertions(+), 1 deletion(-) diff --git a/sources/CPU/CPU.cpp b/sources/CPU/CPU.cpp index 54403c0..6e20259 100644 --- a/sources/CPU/CPU.cpp +++ b/sources/CPU/CPU.cpp @@ -236,6 +236,10 @@ namespace ComSquare::CPU case Instructions::STA_SR: this->STA(this->_getStackRelativeAddr()); return 4 + !this->_registers.p.m; case Instructions::STA_SRYi: this->STA(this->_getStackRelativeIndirectIndexedYAddr()); return 7 + !this->_registers.p.m; + case Instructions::STX_ABS: this->STX(this->_getAbsoluteAddr()); return 4 + !this->_registers.p.m; + case Instructions::STX_DP: this->STX(this->_getAbsoluteAddr()); return 3 + !this->_registers.p.m + this->_registers.dl != 0; + case Instructions::STX_DPY: this->STX(this->_getAbsoluteAddr()); return 4 + !this->_registers.p.m + this->_registers.dl != 0; + default: throw InvalidOpcode("CPU", opcode); } diff --git a/sources/CPU/CPU.hpp b/sources/CPU/CPU.hpp index b8d46c9..4c9a3e0 100644 --- a/sources/CPU/CPU.hpp +++ b/sources/CPU/CPU.hpp @@ -218,7 +218,11 @@ namespace ComSquare::CPU STA_DPYi = 0x91, STA_DPYil = 0x97, STA_SR = 0x83, - STA_SRYi = 0x93 + STA_SRYi = 0x93, + + STX_ABS = 0x8E, + STX_DP = 0x86, + STX_DPY = 0x96 }; //! @brief The main CPU @@ -305,6 +309,8 @@ namespace ComSquare::CPU void ADC(uint24_t valueAddr); //! @brief Store the accumulator to memory. void STA(uint24_t addr); + //! @brief Store the index register X to memory. + void STX(uint24_t addr); public: explicit CPU(std::shared_ptr bus, Cartridge::Header &cartridgeHeader); //! @brief This function continue to execute the Cartridge code. diff --git a/sources/CPU/Instructions/MemoryInstructions.cpp b/sources/CPU/Instructions/MemoryInstructions.cpp index 56bba9a..e8dce2c 100644 --- a/sources/CPU/Instructions/MemoryInstructions.cpp +++ b/sources/CPU/Instructions/MemoryInstructions.cpp @@ -15,4 +15,14 @@ namespace ComSquare::CPU this->_bus->write(addr + 1, this->_registers.ah); } } + + void CPU::STX(uint24_t addr) + { + if (this->_registers.p.x_b) + this->_bus->write(addr, this->_registers.xl); + else { + this->_bus->write(addr, this->_registers.xl); + this->_bus->write(addr + 1, this->_registers.xh); + } + } } \ No newline at end of file diff --git a/tests/CPU/testStore.cpp b/tests/CPU/testStore.cpp index c344c78..7610aac 100644 --- a/tests/CPU/testStore.cpp +++ b/tests/CPU/testStore.cpp @@ -27,4 +27,24 @@ Test(STA, 16bits) pair.second.cpu->STA(0x0); auto data = pair.second.wram->_data[0] + (pair.second.wram->_data[1] << 8u); cr_assert_eq(data, 0x11AB, "The stored value should be 0x11AB but it was 0x%x.", data); +} + +Test(STX, 8bits) +{ + auto pair = Init(); + pair.second.cpu->_registers.p.x_b = true; + pair.second.cpu->_registers.x = 0x11; + pair.second.cpu->STX(0x0); + auto data = pair.second.wram->_data[0]; + cr_assert_eq(data, 0x11, "The stored value should be 0x11 but it was 0x%x.", data); +} + +Test(STX, 16bits) +{ + auto pair = Init(); + pair.second.cpu->_registers.p.x_b = false; + pair.second.cpu->_registers.x = 0x11AB; + pair.second.cpu->STX(0x0); + auto data = pair.second.wram->_data[0] + (pair.second.wram->_data[1] << 8u); + cr_assert_eq(data, 0x11AB, "The stored value should be 0x11AB but it was 0x%x.", data); } \ No newline at end of file From 8cc87d0be248417b3506812ac16a1314750d1b1b Mon Sep 17 00:00:00 2001 From: AnonymusRaccoon Date: Thu, 13 Feb 2020 14:47:55 +0100 Subject: [PATCH 4/7] Adding the STZ --- sources/CPU/CPU.cpp | 15 +++++-- sources/CPU/CPU.hpp | 15 ++++++- .../CPU/Instructions/MemoryInstructions.cpp | 17 ++++++++ tests/CPU/testStore.cpp | 41 +++++++++++++++++++ 4 files changed, 84 insertions(+), 4 deletions(-) diff --git a/sources/CPU/CPU.cpp b/sources/CPU/CPU.cpp index 6e20259..7402b31 100644 --- a/sources/CPU/CPU.cpp +++ b/sources/CPU/CPU.cpp @@ -236,9 +236,18 @@ namespace ComSquare::CPU case Instructions::STA_SR: this->STA(this->_getStackRelativeAddr()); return 4 + !this->_registers.p.m; case Instructions::STA_SRYi: this->STA(this->_getStackRelativeIndirectIndexedYAddr()); return 7 + !this->_registers.p.m; - case Instructions::STX_ABS: this->STX(this->_getAbsoluteAddr()); return 4 + !this->_registers.p.m; - case Instructions::STX_DP: this->STX(this->_getAbsoluteAddr()); return 3 + !this->_registers.p.m + this->_registers.dl != 0; - case Instructions::STX_DPY: this->STX(this->_getAbsoluteAddr()); return 4 + !this->_registers.p.m + this->_registers.dl != 0; + case Instructions::STX_ABS: this->STX(this->_getAbsoluteAddr()); return 4 + !this->_registers.p.m; + case Instructions::STX_DP: this->STX(this->_getDirectAddr()); return 3 + !this->_registers.p.m + this->_registers.dl != 0; + case Instructions::STX_DPY: this->STX(this->_getDirectIndexedByYAddr()); return 4 + !this->_registers.p.m + this->_registers.dl != 0; + + case Instructions::STY_ABS: this->STX(this->_getAbsoluteAddr()); return 4 + !this->_registers.p.m; + case Instructions::STY_DP: this->STX(this->_getDirectAddr()); return 3 + !this->_registers.p.m + this->_registers.dl != 0; + case Instructions::STY_DPX: this->STX(this->_getDirectIndexedByXAddr()); return 4 + !this->_registers.p.m + this->_registers.dl != 0; + + case Instructions::STZ_ABS: this->STX(this->_getAbsoluteAddr()); return 4 + !this->_registers.p.m; + case Instructions::STZ_DP: this->STX(this->_getDirectAddr()); return 3 + !this->_registers.p.m + this->_registers.dl != 0; + case Instructions::STZ_ABSX: this->STX(this->_getAbsoluteIndexedByXAddr()); return 3 + !this->_registers.p.m + this->_registers.dl != 0; + case Instructions::STZ_DPX: this->STX(this->_getDirectIndexedByXAddr()); return 4 + !this->_registers.p.m + this->_registers.dl != 0; default: throw InvalidOpcode("CPU", opcode); diff --git a/sources/CPU/CPU.hpp b/sources/CPU/CPU.hpp index 4c9a3e0..b68ef34 100644 --- a/sources/CPU/CPU.hpp +++ b/sources/CPU/CPU.hpp @@ -222,7 +222,16 @@ namespace ComSquare::CPU STX_ABS = 0x8E, STX_DP = 0x86, - STX_DPY = 0x96 + STX_DPY = 0x96, + + STY_ABS = 0x8C, + STY_DP = 0x84, + STY_DPX = 0x94, + + STZ_ABS = 0x9C, + STZ_DP = 0x64, + STZ_ABSX = 0x9E, + STZ_DPX = 0x74 }; //! @brief The main CPU @@ -311,6 +320,10 @@ namespace ComSquare::CPU void STA(uint24_t addr); //! @brief Store the index register X to memory. void STX(uint24_t addr); + //! @brief Store the index register Y to memory. + void STY(uint24_t addr); + //! @brief Store zero to the memory. + void STZ(uint24_t addr); public: explicit CPU(std::shared_ptr bus, Cartridge::Header &cartridgeHeader); //! @brief This function continue to execute the Cartridge code. diff --git a/sources/CPU/Instructions/MemoryInstructions.cpp b/sources/CPU/Instructions/MemoryInstructions.cpp index e8dce2c..348329e 100644 --- a/sources/CPU/Instructions/MemoryInstructions.cpp +++ b/sources/CPU/Instructions/MemoryInstructions.cpp @@ -25,4 +25,21 @@ namespace ComSquare::CPU this->_bus->write(addr + 1, this->_registers.xh); } } + + void CPU::STY(uint24_t addr) + { + if (this->_registers.p.x_b) + this->_bus->write(addr, this->_registers.yl); + else { + this->_bus->write(addr, this->_registers.yl); + this->_bus->write(addr + 1, this->_registers.yh); + } + } + + void CPU::STZ(uint24_t addr) + { + this->_bus->write(addr, 0x00); + if (!this->_registers.p.m) + this->_bus->write(addr + 1, 0x00); + } } \ No newline at end of file diff --git a/tests/CPU/testStore.cpp b/tests/CPU/testStore.cpp index 7610aac..fae97ba 100644 --- a/tests/CPU/testStore.cpp +++ b/tests/CPU/testStore.cpp @@ -47,4 +47,45 @@ Test(STX, 16bits) pair.second.cpu->STX(0x0); auto data = pair.second.wram->_data[0] + (pair.second.wram->_data[1] << 8u); cr_assert_eq(data, 0x11AB, "The stored value should be 0x11AB but it was 0x%x.", data); +} + +Test(STY, 8bits) +{ + auto pair = Init(); + pair.second.cpu->_registers.p.x_b = true; + pair.second.cpu->_registers.y = 0x11; + pair.second.cpu->STY(0x0); + auto data = pair.second.wram->_data[0]; + cr_assert_eq(data, 0x11, "The stored value should be 0x11 but it was 0x%x.", data); +} + +Test(STY, 16bits) +{ + auto pair = Init(); + pair.second.cpu->_registers.p.x_b = false; + pair.second.cpu->_registers.y = 0x11AB; + pair.second.cpu->STY(0x0); + auto data = pair.second.wram->_data[0] + (pair.second.wram->_data[1] << 8u); + cr_assert_eq(data, 0x11AB, "The stored value should be 0x11AB but it was 0x%x.", data); +} + +Test(STZ, 8bits) +{ + auto pair = Init(); + pair.second.cpu->_registers.p.m = true; + pair.second.wram->_data[0] = 0x11; + pair.second.cpu->STZ(0x0); + auto data = pair.second.wram->_data[0]; + cr_assert_eq(data, 0x00, "The stored value should be 0x00 but it was 0x%x.", data); +} + +Test(STZ, 16bits) +{ + auto pair = Init(); + pair.second.cpu->_registers.p.m = false; + pair.second.wram->_data[0] = 0x11; + pair.second.wram->_data[1] = 0x11; + pair.second.cpu->STZ(0x0); + auto data = pair.second.wram->_data[0] + (pair.second.wram->_data[1] << 8u); + cr_assert_eq(data, 0x00, "The stored value should be 0x00 but it was 0x%x.", data); } \ No newline at end of file From 7e97a9466c6a0d8fd15634c68b63f00a3879e1b9 Mon Sep 17 00:00:00 2001 From: AnonymusRaccoon Date: Thu, 13 Feb 2020 15:50:14 +0100 Subject: [PATCH 5/7] Adding the LDA --- sources/CPU/CPU.cpp | 16 ++++ sources/CPU/CPU.hpp | 20 ++++- .../CPU/Instructions/MemoryInstructions.cpp | 13 ++++ tests/CPU/testStore.cpp | 78 ++++++++++++++++++- 4 files changed, 125 insertions(+), 2 deletions(-) diff --git a/sources/CPU/CPU.cpp b/sources/CPU/CPU.cpp index 7402b31..0b503a3 100644 --- a/sources/CPU/CPU.cpp +++ b/sources/CPU/CPU.cpp @@ -249,6 +249,22 @@ namespace ComSquare::CPU case Instructions::STZ_ABSX: this->STX(this->_getAbsoluteIndexedByXAddr()); return 3 + !this->_registers.p.m + this->_registers.dl != 0; case Instructions::STZ_DPX: this->STX(this->_getDirectIndexedByXAddr()); return 4 + !this->_registers.p.m + this->_registers.dl != 0; + case Instructions::LDA_IM: this->LDA(this->_getImmediateAddr()); return 2 + !this->_registers.p.m; + case Instructions::LDA_ABS: this->LDA(this->_getAbsoluteAddr()); return 4 + !this->_registers.p.m; + case Instructions::LDA_ABSl: this->LDA(this->_getAbsoluteLongAddr()); return 5 + !this->_registers.p.m; + case Instructions::LDA_DP: this->LDA(this->_getDirectAddr()); return 3 + !this->_registers.p.m + this->_registers.dl != 0; + case Instructions::LDA_DPi: this->LDA(this->_getDirectIndirectAddr()); return 5 + !this->_registers.p.m + this->_registers.dl != 0; + case Instructions::LDA_DPil: this->LDA(this->_getDirectIndirectLongAddr()); return 6 + !this->_registers.p.m + this->_registers.dl != 0; + case Instructions::LDA_ABSX: this->LDA(this->_getAbsoluteIndexedByXAddr()); return 4 + !this->_registers.p.m + this->_hasIndexCrossedPageBoundary; + case Instructions::LDA_ABSXl:this->LDA(this->_getAbsoluteIndexedByXLongAddr()); return 5 + !this->_registers.p.m; + case Instructions::LDA_ABSY: this->LDA(this->_getAbsoluteIndexedByYAddr()); return 4 + !this->_registers.p.m + this->_hasIndexCrossedPageBoundary; + case Instructions::LDA_DPX: this->LDA(this->_getDirectIndexedByXAddr()); return 4 + !this->_registers.p.m + this->_registers.dl != 0; + case Instructions::LDA_DPXi: this->LDA(this->_getDirectIndirectIndexedXAddr()); return 6 + !this->_registers.p.m + this->_registers.dl != 0; + case Instructions::LDA_DPYi: this->LDA(this->_getDirectIndirectIndexedYAddr()); return 5 + !this->_registers.p.m + this->_registers.dl != 0 + this->_hasIndexCrossedPageBoundary; + case Instructions::LDA_DPYil:this->LDA(this->_getDirectIndirectIndexedYLongAddr()); return 6 + !this->_registers.p.m + this->_registers.dl != 0; + case Instructions::LDA_SR: this->LDA(this->_getStackRelativeAddr()); return 4 + !this->_registers.p.m; + case Instructions::LDA_SRYi: this->LDA(this->_getStackRelativeIndirectIndexedYAddr()); return 7 + !this->_registers.p.m; + default: throw InvalidOpcode("CPU", opcode); } diff --git a/sources/CPU/CPU.hpp b/sources/CPU/CPU.hpp index b68ef34..26eb30e 100644 --- a/sources/CPU/CPU.hpp +++ b/sources/CPU/CPU.hpp @@ -231,7 +231,23 @@ namespace ComSquare::CPU STZ_ABS = 0x9C, STZ_DP = 0x64, STZ_ABSX = 0x9E, - STZ_DPX = 0x74 + STZ_DPX = 0x74, + + LDA_IM = 0xA9, + LDA_ABS = 0xAD, + LDA_ABSl = 0xAF, + LDA_DP = 0xA5, + LDA_DPi = 0xB2, + LDA_DPil = 0xA7, + LDA_ABSX = 0xBD, + LDA_ABSXl = 0xBF, + LDA_ABSY = 0xB9, + LDA_DPX = 0xB5, + LDA_DPXi = 0xA1, + LDA_DPYi = 0xB1, + LDA_DPYil = 0xB7, + LDA_SR = 0xA3, + LDA_SRYi = 0xB3 }; //! @brief The main CPU @@ -324,6 +340,8 @@ namespace ComSquare::CPU void STY(uint24_t addr); //! @brief Store zero to the memory. void STZ(uint24_t addr); + //! @brief Load the accumulator from memory. + void LDA(uint24_t addr); public: explicit CPU(std::shared_ptr bus, Cartridge::Header &cartridgeHeader); //! @brief This function continue to execute the Cartridge code. diff --git a/sources/CPU/Instructions/MemoryInstructions.cpp b/sources/CPU/Instructions/MemoryInstructions.cpp index 348329e..ac24496 100644 --- a/sources/CPU/Instructions/MemoryInstructions.cpp +++ b/sources/CPU/Instructions/MemoryInstructions.cpp @@ -42,4 +42,17 @@ namespace ComSquare::CPU if (!this->_registers.p.m) this->_bus->write(addr + 1, 0x00); } + + void CPU::LDA(uint24_t addr) + { + if (this->_registers.p.m) { + this->_registers.a = this->_bus->read(addr); + this->_registers.p.n = this->_registers.al & 0xF0u; + } else { + this->_registers.al = this->_bus->read(addr); + this->_registers.ah = this->_bus->read(addr + 1); + this->_registers.p.n = this->_registers.a & 0xF000u; + } + this->_registers.p.z = this->_registers.a == 0x0; + } } \ No newline at end of file diff --git a/tests/CPU/testStore.cpp b/tests/CPU/testStore.cpp index fae97ba..f7dbc5f 100644 --- a/tests/CPU/testStore.cpp +++ b/tests/CPU/testStore.cpp @@ -88,4 +88,80 @@ Test(STZ, 16bits) pair.second.cpu->STZ(0x0); auto data = pair.second.wram->_data[0] + (pair.second.wram->_data[1] << 8u); cr_assert_eq(data, 0x00, "The stored value should be 0x00 but it was 0x%x.", data); -} \ No newline at end of file +} + +Test(LDA, 8bits) +{ + auto pair = Init(); + pair.second.cpu->_registers.p.m = true; + pair.second.wram->_data[0] = 0x01; + pair.second.cpu->LDA(0x0); + auto data = pair.second.cpu->_registers.a; + cr_assert_eq(data, 0x01, "The stored value should be 0x01 but it was 0x%x.", data); + cr_assert_eq(pair.second.cpu->_registers.p.z, false, "The zero flag register should not be set."); + cr_assert_eq(pair.second.cpu->_registers.p.n, false, "The negative flag register should not be set."); +} + +Test(LDA, 8bitsNegative) +{ + auto pair = Init(); + pair.second.cpu->_registers.p.m = true; + pair.second.wram->_data[0] = 0x11; + pair.second.cpu->LDA(0x0); + auto data = pair.second.cpu->_registers.a; + cr_assert_eq(data, 0x11, "The stored value should be 0x11 but it was 0x%x.", data); + cr_assert_eq(pair.second.cpu->_registers.p.z, false, "The zero flag register should not be set."); + cr_assert_eq(pair.second.cpu->_registers.p.n, true, "The negative flag register should be set."); +} + +Test(LDA, 8bitsZero) +{ + auto pair = Init(); + pair.second.cpu->_registers.p.m = true; + pair.second.wram->_data[0] = 0x00; + pair.second.wram->_data[1] = 0x11; + pair.second.cpu->LDA(0x0); + auto data = pair.second.cpu->_registers.a; + cr_assert_eq(data, 0x00, "The stored value should be 0x00 but it was 0x%x.", data); + cr_assert_eq(pair.second.cpu->_registers.p.z, true, "The zero flag register should be set."); + cr_assert_eq(pair.second.cpu->_registers.p.n, false, "The negative flag register should not be set."); +} + +Test(LDA, 16bits) +{ + auto pair = Init(); + pair.second.cpu->_registers.p.m = false; + pair.second.wram->_data[0] = 0xAB; + pair.second.wram->_data[1] = 001; + pair.second.cpu->LDA(0x0); + auto data = pair.second.cpu->_registers.a; + cr_assert_eq(data, 0x01AB, "The stored value should be 0x01AB but it was 0x%x.", data); + cr_assert_eq(pair.second.cpu->_registers.p.z, false, "The zero flag register should not be set."); + cr_assert_eq(pair.second.cpu->_registers.p.n, false, "The negative flag register should not be set."); +} + +Test(LDA, 16bitsNegative) +{ + auto pair = Init(); + pair.second.cpu->_registers.p.m = false; + pair.second.wram->_data[0] = 0xAB; + pair.second.wram->_data[1] = 0x11; + pair.second.cpu->LDA(0x0); + auto data = pair.second.cpu->_registers.a; + cr_assert_eq(data, 0x11AB, "The stored value should be 0x11AB but it was 0x%x.", data); + cr_assert_eq(pair.second.cpu->_registers.p.z, false, "The zero flag register should not be set."); + cr_assert_eq(pair.second.cpu->_registers.p.n, true, "The negative flag register should be set."); +} + +Test(LDA, 16bitsZero) +{ + auto pair = Init(); + pair.second.cpu->_registers.p.m = false; + pair.second.wram->_data[0] = 0x00; + pair.second.wram->_data[1] = 0x00; + pair.second.cpu->LDA(0x0); + auto data = pair.second.cpu->_registers.a; + cr_assert_eq(data, 0x0000, "The stored value should be 0x0000 but it was 0x%x.", data); + cr_assert_eq(pair.second.cpu->_registers.p.z, true, "The zero flag register should be set."); + cr_assert_eq(pair.second.cpu->_registers.p.n, false, "The negative flag register should not be set."); +} From 98eaaa1f0af2657852bf47d0a6724af1d9182ec7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Cl=C3=A9ment=20Le=20Bihan?= Date: Thu, 13 Feb 2020 16:29:48 +0100 Subject: [PATCH 6/7] fix warn --- sources/PPU/PPU.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/sources/PPU/PPU.cpp b/sources/PPU/PPU.cpp index 1e59f57..0bdc94b 100644 --- a/sources/PPU/PPU.cpp +++ b/sources/PPU/PPU.cpp @@ -198,8 +198,8 @@ namespace ComSquare::PPU } PPU::PPU(const std::shared_ptr &bus, Renderer::IRenderer &renderer): - _bus(std::move(bus)), - _renderer(renderer) + _renderer(renderer), + _bus(std::move(bus)) { this->_isLowByte = true; //_vram = new uint16_t[32000]; From f9349cf530366eef27b93fc389651a53d7b1b90b Mon Sep 17 00:00:00 2001 From: AnonymusRaccoon Date: Thu, 13 Feb 2020 16:34:36 +0100 Subject: [PATCH 7/7] The code is now Coplien Compilent --- CMakeLists.txt | 8 ++++---- sources/APU/APU.hpp | 3 +++ sources/APU/DSP/DSP.hpp | 3 +++ sources/CPU/CPU.hpp | 5 ++++- sources/Cartridge/Cartridge.hpp | 9 ++++++++- sources/Memory/IMemory.hpp | 2 +- sources/Memory/MemoryBus.hpp | 5 +++++ sources/Memory/MemoryShadow.hpp | 3 +++ sources/Memory/RectangleShadow.hpp | 3 +++ sources/Models/Int24.hpp | 10 ++++++++++ sources/Models/Ints.hpp | 10 ---------- sources/PPU/PPU.hpp | 4 ++++ sources/Ram/Ram.hpp | 4 ++++ sources/Renderer/NoRenderer.hpp | 3 +++ sources/Renderer/SFRenderer.hpp | 3 +++ sources/SNES.hpp | 3 +++ 16 files changed, 61 insertions(+), 17 deletions(-) create mode 100644 sources/Models/Int24.hpp delete mode 100644 sources/Models/Ints.hpp diff --git a/CMakeLists.txt b/CMakeLists.txt index d3937f0..e0c5967 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -31,8 +31,8 @@ add_executable(unit_tests sources/APU/APU.cpp sources/Exceptions/InvalidAddress.hpp sources/Exceptions/InvalidRom.hpp - sources/Models/Ints.hpp - sources/Models/Ints.hpp + sources/Models/Int24.hpp + sources/Models/Int24.hpp sources/Ram/Ram.cpp sources/Ram/Ram.hpp sources/Memory/MemoryShadow.cpp @@ -93,8 +93,8 @@ add_executable(ComSquare sources/APU/APU.cpp sources/Exceptions/InvalidAddress.hpp sources/Exceptions/InvalidRom.hpp - sources/Models/Ints.hpp - sources/Models/Ints.hpp + sources/Models/Int24.hpp + sources/Models/Int24.hpp sources/Ram/Ram.cpp sources/Ram/Ram.hpp sources/Memory/MemoryShadow.cpp diff --git a/sources/APU/APU.hpp b/sources/APU/APU.hpp index bb903e3..5728a9a 100644 --- a/sources/APU/APU.hpp +++ b/sources/APU/APU.hpp @@ -114,6 +114,9 @@ namespace ComSquare::APU std::shared_ptr _dsp; public: explicit APU(); + APU(const APU &) = default; + APU &operator=(const APU &) = default; + ~APU() = default; //! @brief Read from the internal APU register. //! @param addr The address to read from. The address 0xF0 should refer to the first byte of the register. diff --git a/sources/APU/DSP/DSP.hpp b/sources/APU/DSP/DSP.hpp index 084abca..07f2b8f 100644 --- a/sources/APU/DSP/DSP.hpp +++ b/sources/APU/DSP/DSP.hpp @@ -112,6 +112,9 @@ namespace ComSquare::APU::DSP std::array _channels{}; public: explicit DSP(); + DSP(const DSP &) = default; + DSP &operator=(const DSP &) = default; + ~DSP() = default; //! @brief Read from the internal DSP register. //! @param addr The address to read from. The address 0x0 should refer to the first byte of the register. diff --git a/sources/CPU/CPU.hpp b/sources/CPU/CPU.hpp index 26eb30e..63352da 100644 --- a/sources/CPU/CPU.hpp +++ b/sources/CPU/CPU.hpp @@ -7,7 +7,7 @@ #include "../Memory/IMemory.hpp" #include "../Memory/MemoryBus.hpp" -#include "../Models/Ints.hpp" +#include "../Models/Int24.hpp" #include "Instructions/CommonInstructions.hpp" #include "../Cartridge/Cartridge.hpp" @@ -344,6 +344,9 @@ namespace ComSquare::CPU void LDA(uint24_t addr); public: explicit CPU(std::shared_ptr bus, Cartridge::Header &cartridgeHeader); + CPU(const CPU &) = default; + CPU &operator=(const CPU &) = delete; + ~CPU() = default; //! @brief This function continue to execute the Cartridge code. //! @return The number of CPU cycles that elapsed unsigned update(); diff --git a/sources/Cartridge/Cartridge.hpp b/sources/Cartridge/Cartridge.hpp index 3b6abb2..113619b 100644 --- a/sources/Cartridge/Cartridge.hpp +++ b/sources/Cartridge/Cartridge.hpp @@ -7,7 +7,7 @@ #include #include "../Memory/IMemory.hpp" -#include "../Models/Ints.hpp" +#include "../Models/Int24.hpp" #include "../Memory/IRectangleMemory.hpp" #include "InterruptVectors.hpp" @@ -57,6 +57,9 @@ namespace ComSquare::Cartridge InterruptVectors emulationInterrupts{}; Header() = default; + Header(const Header &) = default; + Header &operator=(const Header &) = default; + ~Header() = default; }; //! @brief Contains the rom's memory/instructions. @@ -86,6 +89,10 @@ namespace ComSquare::Cartridge public: //! @brief Load a rom from it's path. explicit Cartridge(const std::string &romPath); + //! @brief The cartridge can't be copied. + Cartridge(const Cartridge &) = delete; + //! @brief The cartridge can't be assigned. + Cartridge &operator=(const Cartridge &) = delete; //! @brief Destructor that free the cartridge data. ~Cartridge(); diff --git a/sources/Memory/IMemory.hpp b/sources/Memory/IMemory.hpp index 694469d..b0a8e64 100644 --- a/sources/Memory/IMemory.hpp +++ b/sources/Memory/IMemory.hpp @@ -8,7 +8,7 @@ #include #include -#include "../Models/Ints.hpp" +#include "../Models/Int24.hpp" namespace ComSquare::Memory { diff --git a/sources/Memory/MemoryBus.hpp b/sources/Memory/MemoryBus.hpp index b7689eb..e1db314 100644 --- a/sources/Memory/MemoryBus.hpp +++ b/sources/Memory/MemoryBus.hpp @@ -36,6 +36,11 @@ namespace ComSquare inline void _mirrorComponents(SNES &console, unsigned i); public: + MemoryBus() = default; + MemoryBus(const MemoryBus &) = default; + MemoryBus &operator=(const MemoryBus &) = default; + ~MemoryBus() = default; + //! @brief Read data at a global address. //! @param addr The address to read from. //! @return The value that the component returned for this address. If the address was mapped to ram, it simply returned the value. If the address was mapped to a register the component returned the register. diff --git a/sources/Memory/MemoryShadow.hpp b/sources/Memory/MemoryShadow.hpp index e6f4db7..ce80ef8 100644 --- a/sources/Memory/MemoryShadow.hpp +++ b/sources/Memory/MemoryShadow.hpp @@ -17,6 +17,9 @@ namespace ComSquare::Memory public: //! @brief Create a shadow for the memory given as parameter. explicit MemoryShadow(std::shared_ptr initial, uint24_t start, uint24_t end); + MemoryShadow(const MemoryShadow &) = default; + MemoryShadow &operator=(const MemoryShadow &) = default; + ~MemoryShadow() = default; //! @brief Read from the initial IMemory given. //! @param addr The address to read from. The address 0x0 should refer to the first byte of the initial IMemory. diff --git a/sources/Memory/RectangleShadow.hpp b/sources/Memory/RectangleShadow.hpp index c418f24..7f43ad6 100644 --- a/sources/Memory/RectangleShadow.hpp +++ b/sources/Memory/RectangleShadow.hpp @@ -20,6 +20,9 @@ namespace ComSquare::Memory public: //! @brief Create a shadow for the memory given as parameter. explicit RectangleShadow(std::shared_ptr initial, uint8_t startBank, uint8_t endBank, uint16_t startPage, uint16_t endPage); + RectangleShadow(const RectangleShadow &) = default; + RectangleShadow &operator=(const RectangleShadow &) = default; + ~RectangleShadow() = default; //! @brief Internal component read. Implement this as you would implement a basic IMemory's read. //! @param addr The local address to read from. 0x0 refer to the first byte of your data and the address is in the component's space. That means that you can consider this address as continuous diff --git a/sources/Models/Int24.hpp b/sources/Models/Int24.hpp new file mode 100644 index 0000000..6d0f7bd --- /dev/null +++ b/sources/Models/Int24.hpp @@ -0,0 +1,10 @@ +// +// Created by anonymus-raccoon on 1/28/20. +// + +#ifndef COMSQUARE_INT24_HPP +#define COMSQUARE_INT24_HPP + +typedef unsigned uint24_t; + +#endif //COMSQUARE_INT24_HPP diff --git a/sources/Models/Ints.hpp b/sources/Models/Ints.hpp deleted file mode 100644 index 58f6c01..0000000 --- a/sources/Models/Ints.hpp +++ /dev/null @@ -1,10 +0,0 @@ -// -// Created by anonymus-raccoon on 1/28/20. -// - -#ifndef COMSQUARE_INTS_HPP -#define COMSQUARE_INTS_HPP - -typedef unsigned uint24_t; - -#endif //COMSQUARE_INTS_HPP diff --git a/sources/PPU/PPU.hpp b/sources/PPU/PPU.hpp index 41020da..b9d1f84 100644 --- a/sources/PPU/PPU.hpp +++ b/sources/PPU/PPU.hpp @@ -521,6 +521,10 @@ namespace ComSquare::PPU uint16_t *_vram; public: PPU(const std::shared_ptr &bus, Renderer::IRenderer &renderer); + PPU(const PPU &) = default; + PPU &operator=(const PPU &) = delete; + ~PPU() = default; + //! @brief Read data from the component. //! @param addr The local address to read from (0x0 should refer to the first byte of this component). //! @throw This function should thrown an InvalidAddress for address that are not mapped to the component. diff --git a/sources/Ram/Ram.hpp b/sources/Ram/Ram.hpp index 1b15255..1164305 100644 --- a/sources/Ram/Ram.hpp +++ b/sources/Ram/Ram.hpp @@ -18,6 +18,10 @@ namespace ComSquare::Ram public: //! @brief Load a rom from it's path. explicit Ram(size_t size); + //! @brief The ram can't be copied. + Ram(const Ram &) = delete; + //! @brief The ram can't be assigned. + Ram &operator=(Ram &) = delete; //! @brief Destructor that free the ram. ~Ram(); //! @brief Read from the ram. diff --git a/sources/Renderer/NoRenderer.hpp b/sources/Renderer/NoRenderer.hpp index 21269e8..d06d5b1 100644 --- a/sources/Renderer/NoRenderer.hpp +++ b/sources/Renderer/NoRenderer.hpp @@ -29,6 +29,9 @@ namespace ComSquare::Renderer //! @param width width of the window. //! @param maxFPS the number of maximum FPS for the window. NoRenderer(unsigned int height, unsigned int width, int maxFPS); + NoRenderer(const NoRenderer &) = default; + NoRenderer &operator=(const NoRenderer &) = default; + ~NoRenderer() = default; }; } diff --git a/sources/Renderer/SFRenderer.hpp b/sources/Renderer/SFRenderer.hpp index f7b403c..e259fdd 100644 --- a/sources/Renderer/SFRenderer.hpp +++ b/sources/Renderer/SFRenderer.hpp @@ -53,6 +53,9 @@ namespace ComSquare::Renderer //! @param width width of the window. //! @param maxFPS the number of maximum FPS for the window. SFRenderer(unsigned int height, unsigned int width, int maxFPS); + SFRenderer(const SFRenderer &) = delete; + SFRenderer &operator=(const SFRenderer &) = delete; + ~SFRenderer() = default; }; } diff --git a/sources/SNES.hpp b/sources/SNES.hpp index 996cb8a..c863d88 100644 --- a/sources/SNES.hpp +++ b/sources/SNES.hpp @@ -32,6 +32,9 @@ namespace ComSquare std::shared_ptr sram; //! @brief Create all the components using a common memory bus for all of them. SNES(const std::shared_ptr &bus, const std::string &ramPath, Renderer::IRenderer &renderer); + SNES(const SNES &) = default; + SNES &operator=(const SNES &) = default; + ~SNES() = default; }; }