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Adding more tests for the data bus

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This commit is contained in:
AnonymusRaccoon
2020-02-10 17:09:12 +01:00
parent aeb1e127f3
commit f516e7ec66
4 changed files with 66 additions and 20 deletions
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tests/CPU/testAddressingMode.cpp
+50 -11
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@@ -4,6 +4,7 @@
#include <criterion/criterion.h>
#include <bitset>
#include <iostream>
#include "../tests.hpp"
#include "../../sources/SNES.hpp"
using namespace ComSquare;
@@ -19,7 +20,7 @@ Test(AddrMode, Immediate)
{
auto pair = Init();
pair.second.cpu->_registers.pac = 0x000015;
cr_assert_eq(pair.second.cpu->_GetImmediateAddr(), 0x000015, "Got %i, Expected 0x000015");
cr_assert_eq(pair.second.cpu->_getImmediateAddr(), 0x000015, "Got %i, Expected 0x000015");
cr_assert_eq(pair.second.cpu->_registers.pac, 0x000016);
}
@@ -27,16 +28,54 @@ Test(AddrMode, ImmediateBankChange)
{
auto pair = Init();
pair.second.cpu->_registers.pac = 0x00FFFF;
cr_assert_eq(pair.second.cpu->_GetImmediateAddr(), 0x00FFFF);
cr_assert_eq(pair.second.cpu->_getImmediateAddr(), 0x00FFFF);
cr_assert_eq(pair.second.cpu->_registers.pac, 0x010000);
}
//Test(AddrMode, Direct)
//{
// auto pair = Init();
// pair.second.cartridge->_data[0] = 0x15;
// pair.second.cpu->_registers.pac = 0x808000;
// pair.second.cpu->_registers.d = 0x1000;
// cr_assert_eq(pair.second.cpu->_GetDirectAddr(), 0x1015, "Returned address was %i but was expecting 0x1015.");
// cr_assert_eq(pair.second.cpu->_registers.pac, 0x808001);
//}
Test(AddrMode, Direct)
{
auto pair = Init();
pair.second.cartridge->_data[0] = 0x15;
pair.second.cpu->_registers.pac = 0x808000;
pair.second.cpu->_registers.d = 0x1000;
cr_assert_eq(pair.second.cpu->_getDirectAddr(), 0x1015, "Returned address was %i but was expecting 0x1015.",
pair.second.cpu->_getDirectAddr());
cr_assert_eq(pair.second.cpu->_registers.pac, 0x808001);
}
Test(AddrMode, Absolute)
{
auto pair = Init();
pair.second.cartridge->_data[0] = 0x1C;
pair.second.cartridge->_data[1] = 0x90;
pair.second.cpu->_registers.pac = 0x808000;
pair.second.cpu->_registers.dbr = 0x88;
cr_assert_eq(pair.second.cpu->_getAbsoluteAddr(), 0x88901C, "Returned address was %i but was expecting 0x88901C.", pair.second.cpu->_getAbsoluteAddr());
cr_assert_eq(pair.second.cpu->_registers.pac, 0x808002);
}
Test(AddrMode, AbsoluteLong)
{
auto pair = Init();
pair.second.cartridge->_data[0] = 0x1C;
pair.second.cartridge->_data[1] = 0x90;
pair.second.cartridge->_data[1] = 0xFF;
pair.second.cpu->_registers.pac = 0x808000;
pair.second.cpu->_registers.dbr = 0x88;
cr_assert_eq(pair.second.cpu->_getAbsoluteLongAddr(), 0xFF901C, "Returned address was %i but was expecting 0xFF901C.", pair.second.cpu->_getAbsoluteLongAddr());
cr_assert_eq(pair.second.cpu->_registers.pac, 0x808003);
}
Test(AddrMode, DirectIndirectIndexed)
{
auto pair = Init();
pair.second.cartridge->_data[0] = 0x10;
pair.second.sram->_data[0x1000] = 0x30;
pair.second.sram->_data[0x1001] = 0x40;
pair.second.cpu->_registers.pac = 0x808000;
pair.second.cpu->_registers.dbr = 0x80;
pair.second.cpu->_registers.y = 0x0001;
pair.second.cpu->_registers.d = 0x1000;
cr_assert_eq(pair.second.cpu->_getDirectIndirectIndexedAddr(), 0x804031, "Returned address was %i but was expecting 0x804031.", pair.second.cpu->_getDirectIndirectIndexedAddr());
cr_assert_eq(pair.second.cpu->_registers.pac, 0x808001);
}