From fc08e503c895ffa434082334ca8a113d57612e4d Mon Sep 17 00:00:00 2001 From: AnonymusRaccoon Date: Tue, 11 Feb 2020 11:21:12 +0100 Subject: [PATCH] Adding more addressing modes --- sources/CPU/CPU.cpp | 33 +++++++++++++++++++++ sources/CPU/CPU.hpp | 8 ++++++ tests/CPU/testAddressingMode.cpp | 49 ++++++++++++++++++++++++++++++++ 3 files changed, 90 insertions(+) diff --git a/sources/CPU/CPU.cpp b/sources/CPU/CPU.cpp index 155da3f..b84cbc5 100644 --- a/sources/CPU/CPU.cpp +++ b/sources/CPU/CPU.cpp @@ -261,4 +261,37 @@ namespace ComSquare::CPU base += this->_registers.dbr << 16u; return base + this->_registers.y; } + + uint24_t CPU::_getDirectIndirectIndexedLongAddr() + { + uint16_t dp = this->_bus->read(this->_registers.pac++) + this->_registers.d; + uint24_t base = this->_bus->read(dp); + base += this->_bus->read(dp + 1) << 8u; + base += this->_bus->read(dp + 2) << 16u; + return base; + } + + uint24_t CPU::_getDirectIndexedIndirectAddr() + { + uint16_t dp = this->_bus->read(this->_registers.pac++) + this->_registers.d; + dp += this->_registers.x; + uint24_t base = this->_bus->read(dp); + base += this->_bus->read(dp + 1) << 8u; + base += this->_registers.dbr << 16u; + return base; + } + + uint24_t CPU::_getDirectIndexedByXAddr() + { + uint16_t dp = this->_bus->read(this->_registers.pac++) + this->_registers.d; + dp += this->_registers.x; + return dp; + } + + uint24_t CPU::_getDirectIndexedByYAddr() + { + uint16_t dp = this->_bus->read(this->_registers.pac++) + this->_registers.d; + dp += this->_registers.y; + return dp; + } } \ No newline at end of file diff --git a/sources/CPU/CPU.hpp b/sources/CPU/CPU.hpp index 92b51d9..9a06474 100644 --- a/sources/CPU/CPU.hpp +++ b/sources/CPU/CPU.hpp @@ -204,6 +204,14 @@ namespace ComSquare::CPU uint24_t _getAbsoluteLongAddr(); //! @brief The address is DBR:$(read($($Value + D)) + Y). (This functions returns the 24bit space address of the value). uint24_t _getDirectIndirectIndexedAddr(); + //! @brief This mode is like the previous addressing mode, but the difference is that rather than pulling 2 bytes from the DP address, it pulls 3 bytes to form the effective address. + uint24_t _getDirectIndirectIndexedLongAddr(); + //! @brief The direct page address is calculated and added with x. 2 bytes from the dp address combined with DBR will form the effective address. + uint24_t _getDirectIndexedIndirectAddr(); + //! @brief The DP address is added to X to form the effective address. The effective address is always in bank 0. + uint24_t _getDirectIndexedByXAddr(); + //! @brief The DP address is added to Y to form the effective address. The effective address is always in bank 0. + uint24_t _getDirectIndexedByYAddr(); //! @brief Execute a single instruction. diff --git a/tests/CPU/testAddressingMode.cpp b/tests/CPU/testAddressingMode.cpp index d385bfb..5d668f8 100644 --- a/tests/CPU/testAddressingMode.cpp +++ b/tests/CPU/testAddressingMode.cpp @@ -77,4 +77,53 @@ Test(AddrMode, DirectIndirectIndexed) pair.second.cpu->_registers.d = 0x1000; cr_assert_eq(pair.second.cpu->_getDirectIndirectIndexedAddr(), 0x804031, "Returned address was %x but was expecting 0x804031.", pair.second.cpu->_getDirectIndirectIndexedAddr()); cr_assert_eq(pair.second.cpu->_registers.pac, 0x808001); +} + +Test(AddrMode, DirectIndirectIndexedLong) +{ + auto pair = Init(); + pair.second.cpu->_registers.pac = 0x808000; + pair.second.cpu->_registers.d = 0x1000; + pair.second.cartridge->_data[0] = 0x10; + pair.second.wram->_data[0x1010] = 0x30; + pair.second.wram->_data[0x1011] = 0x40; + pair.second.wram->_data[0x1012] = 0x23; + cr_assert_eq(pair.second.cpu->_getDirectIndirectIndexedLongAddr(), 0x234030, "Returned address was %x but was expecting 0x234030.", pair.second.cpu->_getDirectIndirectIndexedLongAddr()); + cr_assert_eq(pair.second.cpu->_registers.pac, 0x808001); +} + +Test(AddrMode, DirectIndexedIndirect) +{ + auto pair = Init(); + pair.second.cartridge->_data[0] = 0x10; + pair.second.cpu->_registers.d = 0x1000; + pair.second.cpu->_registers.x = 0x0002; + pair.second.wram->_data[0x1012] = 0x30; + pair.second.wram->_data[0x1013] = 0x40; + pair.second.cpu->_registers.dbr = 0x80; + pair.second.cpu->_registers.pac = 0x808000; + cr_assert_eq(pair.second.cpu->_getDirectIndexedIndirectAddr(), 0x804030, "Returned address was %x but was expecting 0x804030.", pair.second.cpu->_getDirectIndexedIndirectAddr()); + cr_assert_eq(pair.second.cpu->_registers.pac, 0x808001); +} + +Test(AddrMode, DirectIndexedByX) +{ + auto pair = Init(); + pair.second.cartridge->_data[0] = 0x10; + pair.second.cpu->_registers.d = 0x1000; + pair.second.cpu->_registers.x = 0x0002; + pair.second.cpu->_registers.pac = 0x808000; + cr_assert_eq(pair.second.cpu->_getDirectIndexedByXAddr(), 0x1012, "Returned address was %x but was expecting 0x1012.", pair.second.cpu->_getDirectIndexedByXAddr()); + cr_assert_eq(pair.second.cpu->_registers.pac, 0x808001); +} + +Test(AddrMode, DirectIndexedByY) +{ + auto pair = Init(); + pair.second.cartridge->_data[0] = 0x10; + pair.second.cpu->_registers.d = 0x1000; + pair.second.cpu->_registers.y = 0x0002; + pair.second.cpu->_registers.pac = 0x808000; + cr_assert_eq(pair.second.cpu->_getDirectIndexedByYAddr(), 0x1012, "Returned address was %x but was expecting 0x1012.", pair.second.cpu->_getDirectIndexedByYAddr()); + cr_assert_eq(pair.second.cpu->_registers.pac, 0x808001); } \ No newline at end of file