ComSquare
Registers.hpp
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1 //
2 // Created by Zoe Roux on 2021-07-03.
3 //
4 
5 
6 #pragma once
7 
8 #include "Models/Ints.hpp"
9 
10 namespace ComSquare::CPU
11 {
13  struct Registers
14  {
16  union
17  {
18  struct
19  {
20  uint8_t al;
21  uint8_t ah;
22  };
23  uint16_t a;
24  };
26  uint8_t dbr;
28  union
29  {
30  struct
31  {
32  uint8_t dl;
33  uint8_t dh;
34  };
35  uint16_t d;
36  };
37  union
38  {
39  struct
40  {
42  union
43  {
44  struct
45  {
46  uint8_t pcl;
47  uint8_t pch;
48  };
49  uint16_t pc;
50  };
52  uint8_t pbr;
53  };
55  uint24_t pac;
56  };
58  union
59  {
60  struct
61  {
62  uint8_t sl;
63  uint8_t sh;
64  };
65  uint16_t s;
66  };
68  union
69  {
70  struct
71  {
72  uint8_t xl;
73  uint8_t xh;
74  };
75  uint16_t x;
76  };
78  union
79  {
80  struct
81  {
82  uint8_t yl;
83  uint8_t yh;
84  };
85  uint16_t y;
86  };
87 
89  union
90  {
91  struct
92  {
94  bool c: 1;
96  bool z: 1;
98  bool i: 1;
100  bool d: 1;
102  bool x_b: 1;
104  bool m: 1;
106  bool v: 1;
108  bool n: 1;
109  };
110  uint8_t flags;
111  } p;
112  };
113 
115  struct InternalRegisters
116  {
118  uint8_t nmitimen;
119 
121  uint8_t wrio;
122 
124  uint8_t wrmpya;
126  uint8_t wrmpyb;
127 
129  uint8_t wrdivl;
131  uint8_t wrdivh;
133  uint8_t wrdivb;
134 
136  uint8_t htimel;
138  uint8_t htimeh;
139 
141  uint8_t vtimel;
143  uint8_t vtimeh;
144 
146  uint8_t hdmaen;
147 
149  uint8_t memsel;
150 
152  uint8_t rdnmi;
154  uint8_t timeup;
155 
157  uint8_t hvbjoy;
158 
160  uint8_t rdio;
161 
163  uint8_t rddivl;
165  uint8_t rddivh;
166 
168  uint8_t rdmpyl;
170  uint8_t rdmpyh;
171 
173  uint8_t joy1l;
175  uint8_t joy1h;
176 
178  uint8_t joy2l;
180  uint8_t joy2h;
181 
183  uint8_t joy3l;
185  uint8_t joy3h;
186 
188  uint8_t joy4l;
190  uint8_t joy4h;
191  };
192 }
ComSquare::CPU::Registers::c
bool c
The Carry flag.
Definition: Registers.hpp:94
ComSquare::CPU::InternalRegisters::joy4h
uint8_t joy4h
Controller Port Data Registers (Pad 4 - High)
Definition: Registers.hpp:190
ComSquare::CPU::Registers::sh
uint8_t sh
Definition: Registers.hpp:63
ComSquare::CPU::Registers::dl
uint8_t dl
Definition: Registers.hpp:32
ComSquare::CPU::Registers::d
uint16_t d
Definition: Registers.hpp:35
Ints.hpp
ComSquare::CPU::InternalRegisters::joy4l
uint8_t joy4l
Controller Port Data Registers (Pad 4 - Low)
Definition: Registers.hpp:188
ComSquare::CPU::Registers::yh
uint8_t yh
Definition: Registers.hpp:83
ComSquare::CPU::Registers::v
bool v
The oVerflow flag.
Definition: Registers.hpp:106
ComSquare::CPU::Registers::pc
uint16_t pc
Definition: Registers.hpp:49
ComSquare::CPU::InternalRegisters::joy3h
uint8_t joy3h
Controller Port Data Registers (Pad 3 - High)
Definition: Registers.hpp:185
ComSquare::CPU::InternalRegisters::joy3l
uint8_t joy3l
Controller Port Data Registers (Pad 3 - Low)
Definition: Registers.hpp:183
ComSquare::CPU::InternalRegisters::rdio
uint8_t rdio
IO Port Read Register.
Definition: Registers.hpp:160
ComSquare::CPU::Registers::pbr
uint8_t pbr
The Program Bank Register;.
Definition: Registers.hpp:52
ComSquare::CPU::InternalRegisters::wrio
uint8_t wrio
IO Port Write Register.
Definition: Registers.hpp:121
ComSquare::CPU::InternalRegisters::vtimel
uint8_t vtimel
IRQ Timer Registers (Vertical - Low)
Definition: Registers.hpp:141
ComSquare::CPU::Registers::dbr
uint8_t dbr
The Data Bank Register;.
Definition: Registers.hpp:26
ComSquare::CPU::Registers::i
bool i
The Interrupt request disable flag.
Definition: Registers.hpp:98
ComSquare::CPU::Registers::xh
uint8_t xh
Definition: Registers.hpp:73
ComSquare::CPU::Registers::x_b
bool x_b
The indeX register width flag (in native mode only) - 0 = 16 bits mode, 1 = 8 bits mode OR the Break ...
Definition: Registers.hpp:102
ComSquare::CPU::Registers::pch
uint8_t pch
Definition: Registers.hpp:47
ComSquare::CPU::InternalRegisters::wrdivb
uint8_t wrdivb
Divisor & Dividend Registers (B)
Definition: Registers.hpp:133
ComSquare::CPU
Definition: AddressingModes.cpp:8
ComSquare::CPU::InternalRegisters::rddivl
uint8_t rddivl
Divide Result Registers (can sometimes be used as multiplication result register) - LOW.
Definition: Registers.hpp:163
ComSquare::CPU::InternalRegisters::wrdivh
uint8_t wrdivh
Divisor & Dividend Registers (A - High)
Definition: Registers.hpp:131
ComSquare::CPU::InternalRegisters::htimel
uint8_t htimel
IRQ Timer Registers (Horizontal - Low)
Definition: Registers.hpp:136
ComSquare::CPU::InternalRegisters::joy1l
uint8_t joy1l
Controller Port Data Registers (Pad 1 - Low)
Definition: Registers.hpp:173
uint24_t
unsigned uint24_t
Definition: Ints.hpp:10
ComSquare::CPU::InternalRegisters::rdmpyl
uint8_t rdmpyl
Multiplication Result Registers (can sometimes be used as divide result register) - LOW.
Definition: Registers.hpp:168
ComSquare::CPU::InternalRegisters::timeup
uint8_t timeup
Interrupt Flag Registers - TimeUp.
Definition: Registers.hpp:154
ComSquare::CPU::InternalRegisters::htimeh
uint8_t htimeh
IRQ Timer Registers (Horizontal - High)
Definition: Registers.hpp:138
ComSquare::CPU::InternalRegisters::joy1h
uint8_t joy1h
Controller Port Data Registers (Pad 1 - High)
Definition: Registers.hpp:175
ComSquare::CPU::Registers::z
bool z
The Zero flag.
Definition: Registers.hpp:96
ComSquare::CPU::InternalRegisters::rddivh
uint8_t rddivh
Divide Result Registers (can sometimes be used as multiplication result register) - HIGH.
Definition: Registers.hpp:165
ComSquare::CPU::Registers::n
bool n
The Negative flag.
Definition: Registers.hpp:108
ComSquare::CPU::InternalRegisters::wrdivl
uint8_t wrdivl
Divisor & Dividend Registers (A - Low)
Definition: Registers.hpp:129
ComSquare::CPU::InternalRegisters::hvbjoy
uint8_t hvbjoy
PPU Status Register.
Definition: Registers.hpp:157
ComSquare::CPU::InternalRegisters
Struct containing internal registers of the CPU.
Definition: Registers.hpp:115
ComSquare::CPU::Registers::sl
uint8_t sl
Definition: Registers.hpp:62
ComSquare::CPU::Registers::d
bool d
The Decimal mode flag.
Definition: Registers.hpp:100
ComSquare::CPU::InternalRegisters::memsel
uint8_t memsel
ROM Speed Register.
Definition: Registers.hpp:149
ComSquare::CPU::InternalRegisters::joy2l
uint8_t joy2l
Controller Port Data Registers (Pad 2 - Low)
Definition: Registers.hpp:178
ComSquare::CPU::Registers::flags
uint8_t flags
Definition: Registers.hpp:110
ComSquare::CPU::Registers::m
bool m
The accumulator and Memory width flag (in native mode only) - 0 = 16 bits mode, 1 = 8 bits mode.
Definition: Registers.hpp:104
ComSquare::CPU::Registers::pcl
uint8_t pcl
Definition: Registers.hpp:46
ComSquare::CPU::InternalRegisters::nmitimen
uint8_t nmitimen
Interrupt Enable Register.
Definition: Registers.hpp:118
ComSquare::CPU::Registers::pac
uint24_t pac
The current Program Address Counter (does not exist in a snes but is useful here).
Definition: Registers.hpp:55
ComSquare::CPU::InternalRegisters::rdmpyh
uint8_t rdmpyh
Multiplication Result Registers (can sometimes be used as divide result register) - HIGH.
Definition: Registers.hpp:170
ComSquare::CPU::InternalRegisters::joy2h
uint8_t joy2h
Controller Port Data Registers (Pad 2 - High)
Definition: Registers.hpp:180
ComSquare::CPU::Registers::yl
uint8_t yl
Definition: Registers.hpp:82
ComSquare::CPU::InternalRegisters::vtimeh
uint8_t vtimeh
IRQ Timer Registers (Vertical - High)
Definition: Registers.hpp:143
ComSquare::CPU::Registers
Struct containing registers for the main CPU.
Definition: Registers.hpp:13
ComSquare::CPU::Registers::x
uint16_t x
Definition: Registers.hpp:75
ComSquare::CPU::Registers::dh
uint8_t dh
Definition: Registers.hpp:33
ComSquare::CPU::Registers::y
uint16_t y
Definition: Registers.hpp:85
ComSquare::CPU::Registers::ah
uint8_t ah
Definition: Registers.hpp:21
ComSquare::CPU::Registers::al
uint8_t al
Definition: Registers.hpp:20
ComSquare::CPU::InternalRegisters::wrmpyb
uint8_t wrmpyb
Multiplicand Register B.
Definition: Registers.hpp:126
ComSquare::CPU::InternalRegisters::rdnmi
uint8_t rdnmi
Interrupt Flag Registers.
Definition: Registers.hpp:152
ComSquare::CPU::InternalRegisters::hdmaen
uint8_t hdmaen
HDMA Enable Register.
Definition: Registers.hpp:146
ComSquare::CPU::Registers::s
uint16_t s
Definition: Registers.hpp:65
ComSquare::CPU::Registers::p
union ComSquare::CPU::Registers::@57 p
The Processor status register;.
ComSquare::CPU::Registers::a
uint16_t a
Definition: Registers.hpp:23
ComSquare::CPU::Registers::xl
uint8_t xl
Definition: Registers.hpp:72
ComSquare::CPU::InternalRegisters::wrmpya
uint8_t wrmpya
Multiplicand Register A.
Definition: Registers.hpp:124
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