Class handling all DMA/HDMA transfers (Direct Memory Access or H-Blank Direct Memory Access) More...

#include <DMA.hpp>

Collaboration diagram for ComSquare::CPU::DMA:

Public Types
enum	DMAMode { OneToOne = 0b000, TwoToTwo = 0b001, TwoToOne = 0b010, FourToTwo = 0b011, FourToFour = 0b100, TwoToTwoBis = 0b101, TwoToOneBis = 0b110, FourToTwoBis = 0b111 }
	The first three bytes of the DMA's control register. Used to tell how many bytes/registers there is. More...

enum	Direction { AtoB, BtoA }

Public Member Functions
Memory::IMemoryBus &	getBus ()
	Get the memory bus used by this CPU. More...

void	setBus (Memory::IMemoryBus &bus)
	Set the memory bus used by this CPU. More...

uint8_t	read (uint8_t addr) const
	Bus helper to read from this channel. More...

void	write (uint8_t addr, uint8_t data)
	Bus helper to write to this channel. More...

unsigned	run (unsigned cycles)
	Run the DMA for x cycles. More...

	DMA (Memory::IMemoryBus &bus)
	Create a DMA channel with a given bus. More...

	DMA (const DMA &)=default
	A DMA is copy constructable. More...

DMA &	operator= (const DMA &)=delete
	A DMA is not assignable. More...

	~DMA ()=default
	A default destructor. More...

Public Attributes
bool	enabled
	Is this channel set to run? More...

DMAMode	mode: 3
	DMA's mode: how many bytes/registers there is, how many writes... More...

bool	fixed: 1
	If this flag is set, no increment/decrement will be done. More...

bool	increment: 1
	if this flag is 0: increment. Else: decrement. (The A address) More...

bool	_: 2
	Two unused bites. More...

Direction	direction: 1
	The direction of the transfer. More...

uint8_t	raw

uint8_t	bytes [3]

uint16_t	page

uint8_t	bank

uint24_t	raw: 24

uint16_t	raw

Private Member Functions
unsigned	_writeOneByte (uint24_t aAddress, uint24_t bAddress)
	Write one byte using the A address, the port and the _direction. Handle special cases where no write occurs. More...

int	_getModeOffset (int index) const
	Get an offset corresponding to the current DMAMode and the index of the currently transferred byte. More...

Private Attributes
union {
struct {
DMAMode mode: 3
	DMA's mode: how many bytes/registers there is, how many writes... More...

bool fixed: 1
	If this flag is set, no increment/decrement will be done. More...

bool increment: 1
	if this flag is 0: increment. Else: decrement. (The A address) More...

bool _: 2
	Two unused bites. More...

Direction direction: 1
	The direction of the transfer. More...

}

uint8_t raw

}	_controlRegister
	DMA Control register (various information about the transfer) More...

uint8_t	_port {}
	If this is 'xx', the register accessed will be $21xx. More...

union {
uint8_t bytes [3]

struct {
uint16_t page

uint8_t bank

}

uint24_t raw: 24

}	_aAddress
	The absolute long address of the data from the A bus. More...

union {
uint8_t bytes [2]

uint16_t raw

}	_count
	The number of bytes to be transferred. More...

Memory::IMemoryBus &	_bus
	The memory bus to use for read/write. More...

Detailed Description

Class handling all DMA/HDMA transfers (Direct Memory Access or H-Blank Direct Memory Access)

Member Enumeration Documentation

◆ Direction

enum ComSquare::CPU::DMA::Direction

Enumerator
AtoB
BtoA

◆ DMAMode

enum ComSquare::CPU::DMA::DMAMode

The first three bytes of the DMA's control register. Used to tell how many bytes/registers there is.

Enumerator
OneToOne	1 byte is transferred to 1 register (write once)
TwoToTwo	2 byte is transferred to 2 register (write once)
TwoToOne	2 byte is transferred to 1 register (write twice)
FourToTwo	4 byte is transferred to 2 register (write twice)
FourToFour	4 byte is transferred to 4 register (write once)
TwoToTwoBis	Exactly the same as TwoToTwo (not implemented on the SNES so this fallbacks)
TwoToOneBis	Exactly the same as TwoToOne (not implemented on the SNES so this fallbacks)
FourToTwoBis	Exactly the same as FourToTwo (not implemented on the SNES so this fallbacks)

Constructor & Destructor Documentation

◆ DMA() [1/2]

ComSquare::CPU::DMA::DMA ( Memory::IMemoryBus & bus )

explicit

Create a DMA channel with a given bus.

Parameters

bus	The memory bus to use.

◆ DMA() [2/2]

ComSquare::CPU::DMA::DMA ( const DMA & )

default

A DMA is copy constructable.

◆ ~DMA()

ComSquare::CPU::DMA::~DMA ( )

default

A default destructor.

Member Function Documentation

◆ _getModeOffset()

int ComSquare::CPU::DMA::_getModeOffset ( int index ) const

private

Get an offset corresponding to the current DMAMode and the index of the currently transferred byte.

◆ _writeOneByte()

unsigned ComSquare::CPU::DMA::_writeOneByte	(	uint24_t	aAddress,
		uint24_t	bAddress
	)

private

Write one byte using the A address, the port and the _direction. Handle special cases where no write occurs.

Returns: The number of cycles used.

◆ getBus()

Memory::IMemoryBus& ComSquare::CPU::DMA::getBus ( )

inline

Get the memory bus used by this CPU.

◆ operator=()

DMA& ComSquare::CPU::DMA::operator= ( const DMA & )

delete

A DMA is not assignable.

◆ read()

uint8_t ComSquare::CPU::DMA::read ( uint8_t addr ) const

Bus helper to read from this channel.

Parameters

addr	The address to read from

Returns: The value at the given address.

◆ run()

unsigned ComSquare::CPU::DMA::run ( unsigned cycles )

Run the DMA for x cycles.

Parameters

cycles The maximum number of cycles this DMA should run.

Returns: the number of cycles taken

◆ setBus()

void ComSquare::CPU::DMA::setBus ( Memory::IMemoryBus & bus )

Set the memory bus used by this CPU.

Parameters

bus	The bus to use.

◆ write()

void ComSquare::CPU::DMA::write	(	uint8_t	addr,
		uint8_t	data
	)

Bus helper to write to this channel.

Parameters

addr	The address to write to
data	The data to write.

Member Data Documentation

◆ _

bool ComSquare::CPU::DMA::_

Two unused bites.

◆ _aAddress

union { ... } ComSquare::CPU::DMA::_aAddress

The absolute long address of the data from the A bus.

◆ _bus

Memory::IMemoryBus& ComSquare::CPU::DMA::_bus

private

The memory bus to use for read/write.

◆ _controlRegister

union { ... } ComSquare::CPU::DMA::_controlRegister

DMA Control register (various information about the transfer)

◆ _count

union { ... } ComSquare::CPU::DMA::_count

The number of bytes to be transferred.

◆ _port

uint8_t ComSquare::CPU::DMA::_port {}

private

If this is 'xx', the register accessed will be $21xx.

◆ bank

uint8_t ComSquare::CPU::DMA::bank

◆ bytes

uint8_t ComSquare::CPU::DMA::bytes[2]

◆ direction

Direction ComSquare::CPU::DMA::direction

The direction of the transfer.

◆ enabled

bool ComSquare::CPU::DMA::enabled

Is this channel set to run?

◆ fixed

bool ComSquare::CPU::DMA::fixed

If this flag is set, no increment/decrement will be done.

◆ increment

bool ComSquare::CPU::DMA::increment

if this flag is 0: increment. Else: decrement. (The A address)

◆ mode

DMAMode ComSquare::CPU::DMA::mode

DMA's mode: how many bytes/registers there is, how many writes...

◆ page

uint16_t ComSquare::CPU::DMA::page

◆ raw [1/3]

uint8_t ComSquare::CPU::DMA::raw

◆ raw [2/3]

uint24_t ComSquare::CPU::DMA::raw

◆ raw [3/3]

uint16_t ComSquare::CPU::DMA::raw

The documentation for this class was generated from the following files:

sources/CPU/DMA/DMA.hpp
sources/CPU/DMA/DMA.cpp

Public Types

Public Member Functions

Public Attributes

Private Member Functions

Private Attributes

Detailed Description

Member Enumeration Documentation

◆ Direction

◆ DMAMode

Constructor & Destructor Documentation

◆ DMA() [1/2]

◆ DMA() [2/2]

◆ ~DMA()

Member Function Documentation

◆ _getModeOffset()

◆ _writeOneByte()

◆ getBus()

◆ operator=()

◆ read()

◆ run()

◆ setBus()

◆ write()

Member Data Documentation

◆ _

◆ _aAddress

◆ _bus

◆ _controlRegister

◆ _count

◆ _port

◆ bank

◆ bytes

◆ direction

◆ enabled

◆ fixed

◆ increment

◆ mode

◆ page

◆ raw [1/3]

◆ raw [2/3]

◆ raw [3/3]