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5 #ifndef COMSQUARE_CPU_HPP
6 #define COMSQUARE_CPU_HPP
8 #include "../Memory/IMemory.hpp"
9 #include "../Memory/MemoryBus.hpp"
10 #include "../Models/Ints.hpp"
186 std::shared_ptr<Memory::MemoryBus>
_bus;
192 explicit CPU(std::shared_ptr<Memory::MemoryBus> bus);
209 #endif //COMSQUARE_CPU_HPP
bool b
The Break flag (in emulation mode only)
Definition: CPU.hpp:81
uint8_t joy4h
Controller Port Data Registers (Pad 4 - High)
Definition: CPU.hpp:173
uint8_t sh
Definition: CPU.hpp:47
bool x
The indeX register width flag (in native mode only)
Definition: CPU.hpp:79
uint8_t dl
Definition: CPU.hpp:30
uint16_t d
Definition: CPU.hpp:32
uint8_t joy4l
Controller Port Data Registers (Pad 4 - Low)
Definition: CPU.hpp:171
bool i
The Interrupt disable flag.
Definition: CPU.hpp:86
uint8_t yh
Definition: CPU.hpp:63
uint16_t pc
Definition: CPU.hpp:42
uint8_t joy3h
Controller Port Data Registers (Pad 3 - High)
Definition: CPU.hpp:168
uint8_t joy3l
Controller Port Data Registers (Pad 3 - Low)
Definition: CPU.hpp:166
uint8_t rdio
IO Port Read Register.
Definition: CPU.hpp:143
The main CPU.
Definition: CPU.hpp:177
uint8_t wrio
IO Port Write Register.
Definition: CPU.hpp:101
uint8_t vtimel
IRQ Timer Registers (Vertical - Low)
Definition: CPU.hpp:121
uint8_t dbr
The Data Bank Register;.
Definition: CPU.hpp:25
bool n
The Negative flag.
Definition: CPU.hpp:72
uint8_t xh
Definition: CPU.hpp:55
bool _isEmulationMode
Is the CPU running in emulation mode (in 8bits)
Definition: CPU.hpp:182
void write(uint24_t addr, uint8_t data) override
Write data to the internal CPU register.
Definition: CPU.cpp:86
uint8_t pch
Definition: CPU.hpp:39
uint8_t wrdivb
Divisor & Dividend Registers (B)
Definition: CPU.hpp:113
uint8_t rddivl
Divide Result Registers (can sometimes be used as multiplication result register) - LOW.
Definition: CPU.hpp:146
uint8_t wrdivh
Divisor & Dividend Registers (A - High)
Definition: CPU.hpp:111
uint8_t htimel
IRQ Timer Registers (Horizontal - Low)
Definition: CPU.hpp:116
uint8_t joy1l
Controller Port Data Registers (Pad 1 - Low)
Definition: CPU.hpp:156
unsigned uint24_t
Definition: Ints.hpp:8
uint8_t rdmpyl
Multiplication Result Registers (can sometimes be used as divide result register) - LOW.
Definition: CPU.hpp:151
bool v
The oVerflow flag.
Definition: CPU.hpp:74
Common interface implemented by all components mapping memory.
Definition: IMemory.hpp:16
uint8_t timeup
Interrupt Flag Registers - TimeUp.
Definition: CPU.hpp:137
uint8_t htimeh
IRQ Timer Registers (Horizontal - High)
Definition: CPU.hpp:118
int executeInstruction()
Execute a single instruction.
Definition: CPU.cpp:193
uint8_t k
The program banK register;.
Definition: CPU.hpp:35
bool z
The Zero flag.
Definition: CPU.hpp:88
uint8_t joy1h
Controller Port Data Registers (Pad 1 - High)
Definition: CPU.hpp:158
The Processor status register;.
Definition: CPU.hpp:70
uint8_t rddivh
Divide Result Registers (can sometimes be used as multiplication result register) - HIGH.
Definition: CPU.hpp:148
uint8_t read(uint24_t addr) override
Read from the internal CPU register.
Definition: CPU.cpp:18
uint8_t wrdivl
Divisor & Dividend Registers (A - Low)
Definition: CPU.hpp:109
uint8_t hvbjoy
PPU Status Register.
Definition: CPU.hpp:140
Struct containing internal registers of the CPU.
Definition: CPU.hpp:95
uint8_t sl
Definition: CPU.hpp:48
uint8_t memsel
ROM Speed Register.
Definition: CPU.hpp:132
uint8_t joy2l
Controller Port Data Registers (Pad 2 - Low)
Definition: CPU.hpp:161
InternalRegisters _internalRegisters
Internal registers of the CPU (accessible from the bus via addr $4200 to $421F).
Definition: CPU.hpp:184
uint8_t mdmaen
DMA Enable Register.
Definition: CPU.hpp:126
uint8_t pcl
Definition: CPU.hpp:40
uint8_t nmitimen
Interrupt Enable Register.
Definition: CPU.hpp:98
CPU(std::shared_ptr< Memory::MemoryBus > bus)
Definition: CPU.cpp:13
uint8_t rdmpyh
Multiplication Result Registers (can sometimes be used as divide result register) - HIGH.
Definition: CPU.hpp:153
uint8_t joy2h
Controller Port Data Registers (Pad 2 - High)
Definition: CPU.hpp:163
uint8_t yl
Definition: CPU.hpp:64
uint8_t vtimeh
IRQ Timer Registers (Vertical - High)
Definition: CPU.hpp:123
bool d
The Decimal mode flag.
Definition: CPU.hpp:84
Registers _registers
All the registers of the CPU.
Definition: CPU.hpp:180
Struct containing registers for the main CPU.
Definition: CPU.hpp:15
uint16_t x
Definition: CPU.hpp:58
uint8_t dh
Definition: CPU.hpp:29
uint16_t y
Definition: CPU.hpp:66
uint8_t ah
Definition: CPU.hpp:19
bool m
The accumulator and Memory width flag (in native mode only)
Definition: CPU.hpp:76
uint8_t al
Definition: CPU.hpp:20
uint8_t wrmpyb
Multiplicand Register B.
Definition: CPU.hpp:106
uint8_t rdnmi
Interrupt Flag Registers.
Definition: CPU.hpp:135
uint8_t hdmaen
HDMA Enable Register.
Definition: CPU.hpp:129
uint16_t s
Definition: CPU.hpp:50
bool c
The Carry flag.
Definition: CPU.hpp:90
int update()
This function continue to execute the Cartridge code.
Definition: CPU.cpp:184
uint16_t a
Definition: CPU.hpp:22
uint8_t xl
Definition: CPU.hpp:56
uint8_t wrmpya
Multiplicand Register A.
Definition: CPU.hpp:104
std::shared_ptr< Memory::MemoryBus > _bus
The memory bus to use for read/write.
Definition: CPU.hpp:186