mirror of
https://github.com/zoriya/ComSquare.git
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250 lines
8.1 KiB
C++
250 lines
8.1 KiB
C++
//
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// Created by anonymus-raccoon on 1/24/20.
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//
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#ifndef COMSQUARE_CPU_HPP
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#define COMSQUARE_CPU_HPP
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#include "../Memory/IMemory.hpp"
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#include "../Memory/MemoryBus.hpp"
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#include "../Models/Ints.hpp"
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#include "Instructions/CommonInstructions.hpp"
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#include "../Cartridge/Cartridge.hpp"
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namespace ComSquare::CPU
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{
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//! @brief Struct containing registers for the main CPU.
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struct Registers {
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//! @brief The Accumulator
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union {
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struct {
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uint8_t ah;
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uint8_t al;
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};
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uint16_t a;
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};
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//! @brief The Data Bank Register;
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uint8_t dbr;
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//! @brief The Direct register;
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union {
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struct {
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uint8_t dh;
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uint8_t dl;
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};
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uint16_t d;
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};
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union {
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struct {
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//! @brief The Program Bank Register;
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uint8_t pbr;
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//! @brief The Program Counter;
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union {
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struct {
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uint8_t pch;
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uint8_t pcl;
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};
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uint16_t pc;
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};
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};
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//! @brief The current Program Address Counter (does not exist in a snes but is useful here).
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uint24_t pac;
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};
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//! @brief The Stack pointer
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union {
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struct {
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uint8_t sh;
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uint8_t sl;
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};
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uint16_t s;
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};
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//! @brief The X index register
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union {
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struct {
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uint8_t xh;
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uint8_t xl;
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};
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uint16_t x;
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};
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//! @brief The Y index register
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union {
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struct {
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uint8_t yh;
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uint8_t yl;
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};
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uint16_t y;
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};
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//! @brief The Processor status register;
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union {
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struct {
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//! @brief The Negative flag
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bool n : 1;
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//! @brief The oVerflow flag
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bool v : 1;
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//! @brief The accumulator and Memory width flag (in native mode only)
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bool m : 1;
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//! @brief The indeX register width flag (in native mode only) OR the Break flag (in emulation mode only)
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bool x_b : 1;
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//! @brief The Decimal mode flag
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bool d : 1;
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//! @brief The Interrupt request disable flag
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bool i : 1;
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//! @brief The Zero flag
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bool z : 1;
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//! @brief The Carry flag
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bool c : 1;
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};
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uint8_t flags;
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} p;
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};
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//! @brief Struct containing internal registers of the CPU.
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struct InternalRegisters
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{
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//! @brief Interrupt Enable Register
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uint8_t nmitimen;
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//! @brief IO Port Write Register
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uint8_t wrio;
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//! @brief Multiplicand Register A
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uint8_t wrmpya;
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//! @brief Multiplicand Register B
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uint8_t wrmpyb;
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//! @brief Divisor & Dividend Registers (A - Low)
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uint8_t wrdivl;
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//! @brief Divisor & Dividend Registers (A - High)
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uint8_t wrdivh;
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//! @brief Divisor & Dividend Registers (B)
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uint8_t wrdivb;
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//! @brief IRQ Timer Registers (Horizontal - Low)
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uint8_t htimel;
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//! @brief IRQ Timer Registers (Horizontal - High)
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uint8_t htimeh;
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//! @brief IRQ Timer Registers (Vertical - Low)
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uint8_t vtimel;
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//! @brief IRQ Timer Registers (Vertical - High)
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uint8_t vtimeh;
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//! @brief DMA Enable Register
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uint8_t mdmaen;
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//! @brief HDMA Enable Register
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uint8_t hdmaen;
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//! @brief ROM Speed Register
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uint8_t memsel;
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//! @brief Interrupt Flag Registers
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uint8_t rdnmi;
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//! @brief Interrupt Flag Registers - TimeUp
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uint8_t timeup;
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//! @brief PPU Status Register
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uint8_t hvbjoy;
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//! @brief IO Port Read Register
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uint8_t rdio;
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//! @brief Divide Result Registers (can sometimes be used as multiplication result register) - LOW
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uint8_t rddivl;
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//! @brief Divide Result Registers (can sometimes be used as multiplication result register) - HIGH
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uint8_t rddivh;
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//! @brief Multiplication Result Registers (can sometimes be used as divide result register) - LOW
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uint8_t rdmpyl;
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//! @brief Multiplication Result Registers (can sometimes be used as divide result register) - HIGH
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uint8_t rdmpyh;
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//! @brief Controller Port Data Registers (Pad 1 - Low)
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uint8_t joy1l;
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//! @brief Controller Port Data Registers (Pad 1 - High)
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uint8_t joy1h;
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//! @brief Controller Port Data Registers (Pad 2 - Low)
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uint8_t joy2l;
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//! @brief Controller Port Data Registers (Pad 2 - High)
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uint8_t joy2h;
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//! @brief Controller Port Data Registers (Pad 3 - Low)
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uint8_t joy3l;
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//! @brief Controller Port Data Registers (Pad 3 - High)
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uint8_t joy3h;
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//! @brief Controller Port Data Registers (Pad 4 - Low)
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uint8_t joy4l;
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//! @brief Controller Port Data Registers (Pad 4 - High)
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uint8_t joy4h;
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};
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//! @brief The main CPU
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class CPU : public CommonInstructions, public Memory::IMemory {
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private:
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//! @brief All the registers of the CPU
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Registers _registers{};
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//! @brief Is the CPU running in emulation mode (in 8bits)
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bool _isEmulationMode = true;
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//! @brief Internal registers of the CPU (accessible from the bus via addr $4200 to $421F).
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InternalRegisters _internalRegisters{};
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//! @brief The memory bus to use for read/write.
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std::shared_ptr<Memory::MemoryBus> _bus;
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//! @brief The cartridge header (stored for interrupt vectors..
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Cartridge::Header &_cartridgeHeader;
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//! @brief Immediate address mode is specified with a value. (This functions returns the 24bit space address of the value).
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uint24_t _getImmediateAddr();
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//! @brief The destination is formed by adding the direct page register with the 8-bit address to form an effective address. (This functions returns the 24bit space address of the value).
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uint24_t _getDirectAddr();
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//! @brief The effective address is formed by DBR:<16-bit exp>. (This functions returns the 24bit space address of the value).
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uint24_t _getAbsoluteAddr();
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//! @brief The effective address is the expression. (This functions returns the 24bit space address of the value).
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uint24_t _getAbsoluteLongAddr();
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//! @brief The address is DBR:$(read($($Value + D)) + Y). (This functions returns the 24bit space address of the value).
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uint24_t _getDirectIndirectIndexedAddr();
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//! @brief This mode is like the previous addressing mode, but the difference is that rather than pulling 2 bytes from the DP address, it pulls 3 bytes to form the effective address.
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uint24_t _getDirectIndirectIndexedLongAddr();
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//! @brief The direct page address is calculated and added with x. 2 bytes from the dp address combined with DBR will form the effective address.
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uint24_t _getDirectIndexedIndirectAddr();
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//! @brief The DP address is added to X to form the effective address. The effective address is always in bank 0.
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uint24_t _getDirectIndexedByXAddr();
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//! @brief The DP address is added to Y to form the effective address. The effective address is always in bank 0.
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uint24_t _getDirectIndexedByYAddr();
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//! @brief The absolute expression is added with X and combined with DBR to form the effective address.
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uint24_t _getAbsoluteIndexedByXAddr();
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//! @brief The absolute expression is added with Y and combined with DBR to form the effective address.
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uint24_t _getAbsoluteIndexedByYAddr();
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//! @brief The effective address is formed by adding the <long exp> with X.
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uint24_t _getAbsoluteLongIndexedByXAddr();
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//! @brief Execute a single instruction.
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//! @return The number of CPU cycles that the instruction took.
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int executeInstruction();
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//! @brief Break instruction (0x00) - Causes a software break. The PC is loaded from a vector table.
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int BRK();
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//! @brief Add with carry (0x61, 0x63, 0x65, 0x67, 0x69, 0x6D, 0x6F, 0x71, 0x72, 0x73, 0x75, 0x77, 0x79, 0x7D, 0x7F) - Adds operand to the Accumulator; adds an additional 1 if carry is set.
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int ADC();
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public:
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explicit CPU(std::shared_ptr<Memory::MemoryBus> bus, Cartridge::Header &cartridgeHeader);
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//! @brief This function continue to execute the Cartridge code.
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//! @return The number of CPU cycles that elapsed
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int update();
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//! @brief Read from the internal CPU register.
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//! @param addr The address to read from. The address 0x0 should refer to the first byte of the register.
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//! @throw InvalidAddress will be thrown if the address is more than $1F (the number of register).
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//! @return Return the value of the register.
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uint8_t read(uint24_t addr) override;
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//! @brief Write data to the internal CPU register.
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//! @param addr The address to write to. The address 0x0 should refer to the first byte of register.
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//! @param data The new value of the register.
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//! @throw InvalidAddress will be thrown if the address is more than $1F (the number of register).
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void write(uint24_t addr, uint8_t data) override;
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};
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}
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#endif //COMSQUARE_CPU_HPP
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