mirror of
https://github.com/zoriya/ComSquare.git
synced 2025-12-19 21:55:11 +00:00
370 lines
8.3 KiB
C++
370 lines
8.3 KiB
C++
//
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// Created by Melefo on 27/01/2020.
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//
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#include <cstring>
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#include <iostream>
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#include "APU.hpp"
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#include "../Exceptions/NotImplementedException.hpp"
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#include "../Exceptions/InvalidAddress.hpp"
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#include "../Exceptions/InvalidOpcode.hpp"
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namespace ComSquare::APU
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{
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APU::APU(std::shared_ptr<MemoryMap> &map) :
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_map(map),
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_dsp(new DSP::DSP())
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{
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this->reset();
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}
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bool APU::isDebugger()
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{
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return false;
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}
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uint8_t APU::_internalRead(uint24_t addr) {
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switch (addr) {
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case 0x0000 ... 0x00EF:
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return this->_map->Page0.read_internal(addr);
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case 0xF0:
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return this->_registers.unknown;
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case 0xF2:
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return this->_registers.dspregAddr;
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case 0xF3:
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return this->_registers.dspregData;
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case 0xF4:
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return this->_registers.port0;
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case 0xF5:
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return this->_registers.port1;
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case 0xF6:
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return this->_registers.port2;
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case 0xF7:
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return this->_registers.port3;
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case 0xF8:
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return this->_registers.regmem1;
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case 0xF9:
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return this->_registers.regmem2;
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case 0xFD:
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return this->_registers.counter0;
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case 0xFE:
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return this->_registers.counter1;
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case 0xFF:
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return this->_registers.counter2;
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case 0x0100 ... 0x01FF:
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return this->_map->Page1.read_internal(addr - 0x0100);
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case 0x0200 ... 0xFFBF:
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return this->_map->Memory.read_internal(addr - 0x200);
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case 0xFFC0 ... 0xFFFF:
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return this->_map->IPL.read_internal(addr - 0xFFC0);
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default:
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throw InvalidAddress("APU Registers read", addr);
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}
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}
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void APU::_internalWrite(uint24_t addr, uint8_t data) {
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switch (addr) {
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case 0x0000 ... 0x00EF:
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this->_map->Page0.write_internal(addr, data);
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break;
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case 0xF0:
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this->_registers.unknown = data;
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break;
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case 0xF1:
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this->_registers.ctrlreg = data;
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break;
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case 0xF2:
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this->_registers.dspregAddr = data;
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break;
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case 0xF3:
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this->_registers.dspregData = data;
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break;
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case 0xF4:
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this->_registers.port0 = data;
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break;
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case 0xF5:
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this->_registers.port1 = data;
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break;
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case 0xF6:
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this->_registers.port2 = data;
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break;
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case 0xF7:
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this->_registers.port3 = data;
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break;
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case 0xF8:
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this->_registers.regmem1 = data;
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break;
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case 0xF9:
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this->_registers.regmem2 = data;
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break;
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case 0xFA:
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this->_registers.timer0 = data;
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break;
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case 0xFB:
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this->_registers.timer1 = data;
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break;
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case 0xFC:
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this->_registers.timer2 = data;
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break;
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case 0x0100 ... 0x01FF:
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this->_map->Page1.write_internal(addr - 0x0100, data);
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break;
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case 0x0200 ... 0xFFBF:
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this->_map->Memory.write_internal(addr - 0x200, data);
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break;
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case 0xFFC0 ... 0xFFFF:
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this->_map->IPL.write_internal(addr - 0xFFC0, data);
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break;
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default:
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throw InvalidAddress("APU Registers write", addr);
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}
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}
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uint8_t APU::read(uint24_t addr)
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{
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switch (addr) {
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case 0x00:
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return this->_registers.port0;
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case 0x01:
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return this->_registers.port1;
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case 0x02:
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return this->_registers.port2;
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case 0x03:
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return this->_registers.port3;
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default:
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throw InvalidAddress("APU Registers read", addr);
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}
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}
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void APU::write(uint24_t addr, uint8_t data)
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{
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switch (addr) {
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case 0x00:
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this->_registers.port0 = data;
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break;
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case 0x01:
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this->_registers.port1 = data;
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break;
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case 0x02:
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this->_registers.port2 = data;
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break;
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case 0x03:
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this->_registers.port3 = data;
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break;
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default:
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throw InvalidAddress("APU Registers write", addr);
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}
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}
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void APU::reset()
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{
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}
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int APU::_executeInstruction()
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{
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uint8_t opcode = this->_internalRead(this->_internalRegisters.pc);
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switch (opcode) {
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case 0x00:
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return this->NOP();
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case 0x01:
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return this->TCALL(0);
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case 0x02:
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return this->SET1(this->_getDirectAddr(), 0);
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case 0x0A:
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return this->OR1(this->_getAbsoluteBit());
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case 0x0D:
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return this->PUSH(this->_internalRegisters.psw);
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case 0x0E:
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return this->TSET1(this->_getAbsoluteAddr());
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case 0x0F:
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return this->BRK();
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case 0x10:
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return this->BPL();
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case 0x11:
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return this->TCALL(1);
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case 0x12:
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return this->CLR1(this->_getDirectAddr(), 0);
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case 0x20:
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return this->CLRP();
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case 0x21:
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return this->TCALL(2);
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case 0x22:
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return this->SET1(this->_getDirectAddr(), 1);
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case 0x2A:
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return this->OR1(this->_getAbsoluteBit(), true);
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case 0x2D:
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return this->PUSH(this->_internalRegisters.a);
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case 0x2F:
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return this->BRA();
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case 0x30:
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return this->BMI();
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case 0x31:
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return this->TCALL(3);
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case 0x32:
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return this->CLR1(this->_getDirectAddr(), 1);
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case 0x3F:
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return this->CALL(this->_getAbsoluteAddr());
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case 0x40:
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return this->SETP();
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case 0x41:
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return this->TCALL(4);
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case 0x42:
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return this->SET1(this->_getDirectAddr(), 2);
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case 0x4A:
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return this->AND1(this->_getAbsoluteBit());
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case 0x4D:
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return this->PUSH(this->_internalRegisters.x);
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case 0x4E:
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return this->TCLR1(this->_getAbsoluteAddr());
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case 0x4F:
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return this->PCALL();
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case 0x50:
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return this->BVC();
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case 0x51:
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return this->TCALL(5);
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case 0x52:
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return this->CLR1(this->_getDirectAddr(), 2);
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case 0x60:
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return this->CLRC();
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case 0x61:
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return this->TCALL(6);
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case 0x62:
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return this->SET1(this->_getDirectAddr(), 3);
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case 0x6A:
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return this->AND1(this->_getAbsoluteBit(), true);
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case 0x6D:
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return this->PUSH(this->_internalRegisters.y);
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case 0x6F:
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return this->RET();
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case 0x70:
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return this->BVS();
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case 0x71:
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return this->TCALL(7);
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case 0x72:
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return this->CLR1(this->_getDirectAddr(), 3);
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case 0x7F:
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return this->RETI();
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case 0x80:
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return this->SETC();
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case 0x81:
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return this->TCALL(8);
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case 0x82:
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return this->SET1(this->_getDirectAddr(), 4);
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case 0x8A:
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return this->EOR1(this->_getAbsoluteBit());
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case 0x8E:
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return this->POP(this->_internalRegisters.psw);
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case 0x90:
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return this->BCC();
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case 0x91:
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return this->TCALL(9);
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case 0x92:
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return this->CLR1(this->_getDirectAddr(), 4);
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case 0xA0:
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return this->EI();
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case 0xA1:
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return this->TCALL(10);
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case 0xA2:
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return this->SET1(this->_getDirectAddr(), 5);
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case 0xAA:
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return this->MOV1(this->_getAbsoluteBit(), true);
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case 0xAE:
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return this->POP(this->_internalRegisters.a);
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case 0xB0:
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return this->BCS();
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case 0xB1:
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return this->TCALL(11);
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case 0xB2:
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return this->CLR1(this->_getDirectAddr(), 5);
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case 0xC0:
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return this->DI();
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case 0xC1:
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return this->TCALL(12);
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case 0xC2:
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return this->SET1(this->_getDirectAddr(), 6);
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case 0xCA:
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return this->MOV1(this->_getAbsoluteBit());
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case 0xCE:
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return this->POP(this->_internalRegisters.x);
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case 0xD0:
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return this->BNE();
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case 0xD1:
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return this->TCALL(13);
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case 0xD2:
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return this->CLR1(this->_getDirectAddr(), 6);
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case 0xE1:
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return this->TCALL(14);
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case 0xE2:
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return this->SET1(this->_getDirectAddr(), 7);
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case 0xEE:
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return this->POP(this->_internalRegisters.y);
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case 0xF0:
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return BEQ();
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case 0xF1:
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return this->TCALL(15);
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case 0xF2:
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return this->CLR1(this->_getDirectAddr(), 7);
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case 0xEA:
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return this->NOT1(this->_getAbsoluteBit());
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case 0xED:
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return this->NOTC();
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case 0xEF:
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return this->SLEEP();
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case 0xFF:
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return this->STOP();
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default:
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throw InvalidOpcode("APU", opcode);
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}
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}
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void APU::update(unsigned cycles)
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{
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unsigned total = 0;
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cycles -= this->_paddingCycles;
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while (total < cycles && this->_state == Running)
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total += this->_executeInstruction();
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if (this->_state == Running)
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this->_paddingCycles = total - cycles;
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}
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uint24_t APU::_getDirectAddr()
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{
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uint24_t addr = this->_internalRead(this->_internalRegisters.pc++);
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if (this->_internalRegisters.p)
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addr += 0x100;
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return addr;
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}
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uint24_t APU::_getAbsoluteAddr()
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{
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uint24_t addr1 = this->_internalRead(this->_internalRegisters.pc++);
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uint24_t addr2 = this->_internalRead(this->_internalRegisters.pc++);
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return (addr2 << 8u) | addr1;
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}
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std::pair<uint24_t, uint24_t> APU::_getAbsoluteBit()
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{
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uint24_t addr1 = this->_internalRead(this->_internalRegisters.pc++);
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uint24_t addr2 = this->_internalRead(this->_internalRegisters.pc++);
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uint24_t operandA = (addr2 << 8u) | addr1;
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uint24_t operandB = operandA >> 13u;
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operandA = operandA & 0x1FFFu;
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return std::make_pair(operandA, operandB);
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}
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MemoryMap::MemoryMap() :
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Page0(0x00F0, "APU's Page 0"),
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Page1(0x0100, "APU's Page 1"),
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Memory(0xFDC0, "APU's Ram"),
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IPL(0x0040, "IPL Rom")
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{
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}
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}
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