mirror of
https://github.com/zoriya/ComSquare.git
synced 2025-12-20 22:25:11 +00:00
355 lines
8.5 KiB
C++
355 lines
8.5 KiB
C++
//
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// Created by anonymus-raccoon on 1/24/20.
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//
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#include "CPU.hpp"
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#include "Exceptions/InvalidAddress.hpp"
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#include "Exceptions/InvalidOpcode.hpp"
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#include "Utility/Utility.hpp"
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#include <iostream>
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namespace ComSquare::CPU
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{
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CPU::CPU(Memory::MemoryBus &bus, Cartridge::Header &cartridgeHeader)
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: _bus(bus),
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_cartridgeHeader(cartridgeHeader),
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_dmaChannels({DMA(bus), DMA(bus), DMA(bus), DMA(bus), DMA(bus), DMA(bus), DMA(bus), DMA(bus)})
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{
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this->RESB();
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}
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//! @bref The CPU's internal registers starts at $4200 and finish at $421F.
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uint8_t CPU::read(uint24_t addr)
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{
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uint8_t tmp = 0;
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switch (addr) {
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case 0x0:
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return this->_internalRegisters.nmitimen;
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case 0x1:
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return this->_internalRegisters.wrio;
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case 0x2:
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return this->_internalRegisters.wrmpya;
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case 0x3:
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return this->_internalRegisters.wrmpyb;
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case 0x4:
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return this->_internalRegisters.wrdivl;
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case 0x5:
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return this->_internalRegisters.wrdivh;
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case 0x6:
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return this->_internalRegisters.wrdivb;
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case 0x7:
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return this->_internalRegisters.htimel;
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case 0x8:
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return this->_internalRegisters.htimeh;
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case 0x9:
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return this->_internalRegisters.vtimel;
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case 0xA:
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return this->_internalRegisters.vtimeh;
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case 0xB:
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for (int i = 0; i < 8; i++)
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tmp |= this->_dmaChannels[i].enabled << i;
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return tmp;
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case 0xC:
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return this->_internalRegisters.hdmaen;
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case 0xD:
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return this->_internalRegisters.memsel;
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case 0x10:
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return this->_internalRegisters.rdnmi;
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case 0x11:
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return this->_internalRegisters.timeup;
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case 0x12:
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return this->_internalRegisters.hvbjoy;
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case 0x13:
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return this->_internalRegisters.rdio;
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case 0x14:
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return this->_internalRegisters.rddivl;
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case 0x15:
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return this->_internalRegisters.rddivh;
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case 0x16:
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return this->_internalRegisters.rdmpyl;
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case 0x17:
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return this->_internalRegisters.rdmpyh;
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case 0x18:
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return this->_internalRegisters.joy1l;
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case 0x19:
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return this->_internalRegisters.joy1h;
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case 0x1A:
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return this->_internalRegisters.joy2l;
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case 0x1B:
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return this->_internalRegisters.joy2h;
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case 0x1C:
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return this->_internalRegisters.joy3l;
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case 0x1D:
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return this->_internalRegisters.joy3h;
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case 0x1E:
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return this->_internalRegisters.joy4l;
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case 0x1F:
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return this->_internalRegisters.joy4h;
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case 0x100 ... 0x180:
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return this->_dmaChannels[(addr - 0x100) >> 8u].read(addr & 0xF);
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default:
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throw InvalidAddress("CPU Internal Registers read", addr + this->_start);
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}
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}
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void CPU::write(uint24_t addr, uint8_t data)
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{
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switch (addr) {
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case 0x0:
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this->_internalRegisters.nmitimen = data;
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break;
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case 0x1:
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this->_internalRegisters.wrio = data;
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break;
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case 0x2:
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this->_internalRegisters.wrmpya = data;
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break;
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case 0x3:
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this->_internalRegisters.wrmpyb = data;
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break;
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case 0x4:
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this->_internalRegisters.wrdivl = data;
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break;
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case 0x5:
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this->_internalRegisters.wrdivh = data;
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break;
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case 0x6:
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this->_internalRegisters.wrdivb = data;
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break;
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case 0x7:
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this->_internalRegisters.htimel = data;
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break;
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case 0x8:
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this->_internalRegisters.htimeh = data;
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break;
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case 0x9:
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this->_internalRegisters.vtimel = data;
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break;
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case 0xA:
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this->_internalRegisters.vtimeh = data;
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break;
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case 0xB:
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for (int i = 0; i < 8; i++)
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this->_dmaChannels[i].enabled = data & (0b1 << i);
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break;
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case 0xC:
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this->_internalRegisters.hdmaen = data;
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break;
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case 0xD:
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this->_internalRegisters.memsel = data;
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break;
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case 0x10:
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this->_internalRegisters.rdnmi = data;
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break;
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case 0x11:
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this->_internalRegisters.timeup = data;
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break;
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case 0x12:
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this->_internalRegisters.hvbjoy = data;
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break;
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case 0x13:
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this->_internalRegisters.rdio = data;
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break;
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case 0x14:
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this->_internalRegisters.rddivl = data;
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break;
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case 0x15:
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this->_internalRegisters.rddivh = data;
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break;
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case 0x16:
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this->_internalRegisters.rdmpyl = data;
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break;
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case 0x17:
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this->_internalRegisters.rdmpyh = data;
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break;
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case 0x18:
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this->_internalRegisters.joy1l = data;
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break;
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case 0x19:
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this->_internalRegisters.joy1h = data;
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break;
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case 0x1A:
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this->_internalRegisters.joy2l = data;
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break;
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case 0x1B:
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this->_internalRegisters.joy2h = data;
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break;
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case 0x1C:
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this->_internalRegisters.joy3l = data;
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break;
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case 0x1D:
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this->_internalRegisters.joy3h = data;
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break;
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case 0x1E:
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this->_internalRegisters.joy4l = data;
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break;
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case 0x1F:
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this->_internalRegisters.joy4h = data;
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break;
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case 0x100 ... 0x180:
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this->_dmaChannels[(addr - 0x100) >> 8u].write(addr & 0xF, data);
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break;
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default:
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throw InvalidAddress("CPU Internal Registers write", addr + this->_start);
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}
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}
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uint24_t CPU::getSize() const
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{
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return 0x180;
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}
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uint8_t CPU::readPC()
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{
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uint8_t ret = this->_bus.read(this->_registers.pac);
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this->_registers.pc++;
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return ret;
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}
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unsigned CPU::update()
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{
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unsigned cycles = 0;
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const unsigned maxCycles = 0x0C;
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for (DMA &channel : this->_dmaChannels) {
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if (!channel.enabled)
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continue;
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cycles += channel.run(maxCycles - cycles);
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}
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for (unsigned i = 0; i < maxCycles; i++) {
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if (this->_isStopped) {
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cycles += 1;
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continue;
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}
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this->_checkInterrupts();
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if (!this->_isWaitingForInterrupt)
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cycles += this->_executeInstruction(this->readPC());
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}
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return cycles;
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}
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void CPU::_checkInterrupts()
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{
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if (!this->IsNMIRequested && !this->IsIRQRequested && !this->IsAbortRequested)
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return;
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this->_isWaitingForInterrupt = false;
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if (this->IsNMIRequested) {
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this->_runInterrupt(
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this->_cartridgeHeader.nativeInterrupts.nmi,
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this->_cartridgeHeader.emulationInterrupts.nmi);
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return;
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}
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if (this->IsIRQRequested && !this->_registers.p.i) {
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this->_runInterrupt(
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this->_cartridgeHeader.nativeInterrupts.irq,
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this->_cartridgeHeader.emulationInterrupts.irq);
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return;
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}
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}
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uint24_t CPU::_getValueAddr(Instruction &instruction)
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{
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switch (instruction.addressingMode) {
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case Implied:
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return 0;
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case Immediate8bits:
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return this->_getImmediateAddr8Bits();
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case Immediate16bits:
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return this->_getImmediateAddr16Bits();
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case ImmediateForA:
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return this->_getImmediateAddrForA();
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case ImmediateForX:
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return this->_getImmediateAddrForX();
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case Absolute:
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return this->_getAbsoluteAddr();
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case AbsoluteLong:
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return this->_getAbsoluteLongAddr();
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case AbsoluteIndirect:
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return this->_getAbsoluteIndirectAddr();
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case AbsoluteIndirectLong:
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return this->_getAbsoluteIndirectLongAddr();
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case DirectPage:
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return this->_getDirectAddr();
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case DirectPageIndirect:
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return this->_getDirectIndirectAddr();
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case DirectPageIndirectLong:
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return this->_getDirectIndirectLongAddr();
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case DirectPageIndexedByX:
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return this->_getDirectIndexedByXAddr();
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case DirectPageIndexedByY:
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return this->_getDirectIndexedByYAddr();
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case DirectPageIndirectIndexedByX:
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return this->_getDirectIndirectIndexedXAddr();
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case DirectPageIndirectIndexedByY:
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return this->_getDirectIndirectIndexedYAddr();
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case DirectPageIndirectIndexedByYLong:
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return this->_getDirectIndirectIndexedYLongAddr();
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case AbsoluteIndexedByX:
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return this->_getAbsoluteIndexedByXAddr();
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case AbsoluteIndexedByXLong:
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return this->_getAbsoluteIndexedByXLongAddr();
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case AbsoluteIndexedByY:
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return this->_getAbsoluteIndexedByYAddr();
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case StackRelative:
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return this->_getStackRelativeAddr();
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case StackRelativeIndirectIndexedByY:
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return this->_getStackRelativeIndirectIndexedYAddr();
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case AbsoluteIndirectIndexedByX:
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return this->_getAbsoluteIndirectIndexedByXAddr();
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}
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throw InvalidOpcode("Unknown addressing mode for.");
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}
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unsigned CPU::_executeInstruction(uint8_t opcode)
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{
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Instruction instruction = this->_instructions[opcode];
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this->_hasIndexCrossedPageBoundary = false;
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uint24_t valueAddr = this->_getValueAddr(instruction);
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return instruction.cycleCount + (this->*instruction.call)(valueAddr, instruction.addressingMode);
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}
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void CPU::_push(uint8_t data)
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{
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this->_bus.write(this->_registers.s--, data);
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}
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void CPU::_push(uint16_t data)
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{
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this->_bus.write(this->_registers.s--, data >> 8u);
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this->_bus.write(this->_registers.s--, data);
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}
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uint8_t CPU::_pop()
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{
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return this->_bus.read(++this->_registers.s);
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}
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uint16_t CPU::_pop16()
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{
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uint16_t value = this->_bus.read(++this->_registers.s);
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value += this->_bus.read(++this->_registers.s) << 8u;
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return value;
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}
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std::string CPU::getName() const
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{
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return "CPU";
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}
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Component CPU::getComponent() const
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{
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return Cpu;
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}
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}// namespace ComSquare::CPU
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