mirror of
https://github.com/zoriya/ComSquare.git
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128 lines
2.8 KiB
C++
128 lines
2.8 KiB
C++
//
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// Created by anonymus-raccoon on 5/26/20.
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//
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#include "DMA.hpp"
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#include "Exceptions/InvalidAddress.hpp"
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namespace ComSquare::CPU
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{
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DMA::DMA(Memory::MemoryBus &bus)
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: _bus(bus),
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enabled(false)
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{}
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uint8_t DMA::read(uint8_t addr) const
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{
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switch (addr) {
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case 0x0:
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return this->_controlRegister.raw;
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case 0x1:
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return this->_port;
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case 0x2:
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return this->_aAddress.bytes[0];
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case 0x3:
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return this->_aAddress.bytes[1];
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case 0x4:
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return this->_aAddress.bytes[2];
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case 0x5:
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return this->_count.bytes[0];
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case 0x6:
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return this->_count.bytes[1];
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default:
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throw InvalidAddress("DMA read", addr);
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}
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}
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void DMA::write(uint8_t addr, uint8_t data)
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{
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switch (addr) {
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case 0x0:
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this->_controlRegister.raw = data;
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break;
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case 0x1:
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this->_port = data;
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break;
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case 0x2:
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this->_aAddress.bytes[0] = data;
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break;
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case 0x3:
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this->_aAddress.bytes[1] = data;
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break;
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case 0x4:
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this->_aAddress.bytes[2] = data;
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break;
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case 0x5:
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this->_count.bytes[0] = data;
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break;
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case 0x6:
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this->_count.bytes[1] = data;
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break;
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default:
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throw InvalidAddress("DMA read", addr);
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}
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}
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unsigned DMA::_writeOneByte(uint24_t aAddress, uint24_t bAddress)
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{
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// Address $2180 refers to the WRam data register.
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// Write to/Read from this port when the a address is on the vram cause different behaviors.
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if (this->_port == 0x80) {
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auto accessor = this->_bus.getAccessor(aAddress);
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if (accessor && accessor->getComponent() == WRam) {
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// WRAM->$2180 The write is not performed but the time is consumed anyway.
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if (this->_controlRegister.direction == AtoB)
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return 8;
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// $2180->WRAM No read is performed (so only 4 master cycles are needed) but the value written is invalid.
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this->_bus.write(aAddress, 0xFF);
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return 4;
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}
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}
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if (this->_controlRegister.direction == AtoB) {
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uint8_t data = this->_bus.read(aAddress);
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this->_bus.write(bAddress, data);
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} else {
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uint8_t data = this->_bus.read(bAddress);
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this->_bus.write(aAddress, data);
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}
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return 8;
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}
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unsigned DMA::run(unsigned int maxCycles)
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{
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unsigned cycles = 8;
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int i = 0;
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do {
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cycles += this->_writeOneByte(this->_aAddress.raw, 0x2100 | (this->_port + this->_getModeOffset(i)));
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if (!this->_controlRegister.fixed)
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this->_aAddress.page += this->_controlRegister.increment ? -1 : 1;
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this->_count.raw--;
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i++;
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} while (this->_count.raw > 0 && this->enabled);
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this->enabled = false;
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return cycles;
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}
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int DMA::_getModeOffset(int index) const
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{
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switch (this->_controlRegister.mode) {
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case OneToOne:
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case TwoToOne:
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case TwoToOneBis:
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return 0;
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case TwoToTwo:
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case TwoToTwoBis:
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return index % 2;
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case FourToTwo:
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case FourToTwoBis:
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return (index & 0b11) > 1;
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case FourToFour:
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return (index & 0b11);
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}
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return 0;
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}
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}// namespace ComSquare::CPU
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