mirror of
https://github.com/zoriya/ComSquare.git
synced 2025-12-19 21:55:11 +00:00
455 lines
12 KiB
C++
455 lines
12 KiB
C++
//
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// Created by anonymus-raccoon on 1/24/20.
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//
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#include "CPU.hpp"
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#include <utility>
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#include <iostream>
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#include "../Exceptions/NotImplementedException.hpp"
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#include "../Exceptions/InvalidAddress.hpp"
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#include "../Exceptions/InvalidOpcode.hpp"
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namespace ComSquare::CPU
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{
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CPU::CPU(std::shared_ptr<Memory::MemoryBus> bus, Cartridge::Header &cartridgeHeader)
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: _bus(std::move(bus)), _cartridgeHeader(cartridgeHeader)
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{
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this->RESB();
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}
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//! @bref The CPU's internal registers starts at $4200 and finish at $421F.
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uint8_t CPU::read(uint24_t addr)
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{
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switch (addr) {
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case 0x0:
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return this->_internalRegisters.nmitimen;
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case 0x1:
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return this->_internalRegisters.wrio;
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case 0x2:
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return this->_internalRegisters.wrmpya;
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case 0x3:
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return this->_internalRegisters.wrmpyb;
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case 0x4:
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return this->_internalRegisters.wrdivl;
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case 0x5:
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return this->_internalRegisters.wrdivh;
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case 0x6:
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return this->_internalRegisters.wrdivb;
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case 0x7:
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return this->_internalRegisters.htimel;
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case 0x8:
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return this->_internalRegisters.htimeh;
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case 0x9:
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return this->_internalRegisters.vtimel;
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case 0xA:
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return this->_internalRegisters.vtimeh;
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case 0xB:
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return this->_internalRegisters.mdmaen;
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case 0xC:
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return this->_internalRegisters.hdmaen;
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case 0xD:
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return this->_internalRegisters.memsel;
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case 0x10:
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return this->_internalRegisters.rdnmi;
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case 0x11:
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return this->_internalRegisters.timeup;
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case 0x12:
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return this->_internalRegisters.hvbjoy;
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case 0x13:
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return this->_internalRegisters.rdio;
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case 0x14:
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return this->_internalRegisters.rddivl;
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case 0x15:
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return this->_internalRegisters.rddivh;
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case 0x16:
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return this->_internalRegisters.rdmpyl;
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case 0x17:
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return this->_internalRegisters.rdmpyh;
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case 0x18:
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return this->_internalRegisters.joy1l;
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case 0x19:
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return this->_internalRegisters.joy1h;
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case 0x1A:
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return this->_internalRegisters.joy2l;
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case 0x1B:
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return this->_internalRegisters.joy2h;
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case 0x1C:
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return this->_internalRegisters.joy3l;
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case 0x1D:
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return this->_internalRegisters.joy3h;
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case 0x1E:
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return this->_internalRegisters.joy4l;
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case 0x1F:
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return this->_internalRegisters.joy4h;
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default:
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throw InvalidAddress("CPU Internal Registers read", addr);
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}
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}
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void CPU::write(uint24_t addr, uint8_t data)
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{
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switch (addr) {
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case 0x0:
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this->_internalRegisters.nmitimen = data;
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break;
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case 0x1:
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this->_internalRegisters.wrio = data;
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break;
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case 0x2:
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this->_internalRegisters.wrmpya = data;
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break;
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case 0x3:
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this->_internalRegisters.wrmpyb = data;
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break;
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case 0x4:
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this->_internalRegisters.wrdivl = data;
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break;
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case 0x5:
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this->_internalRegisters.wrdivh = data;
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break;
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case 0x6:
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this->_internalRegisters.wrdivb = data;
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break;
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case 0x7:
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this->_internalRegisters.htimel = data;
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break;
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case 0x8:
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this->_internalRegisters.htimeh = data;
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break;
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case 0x9:
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this->_internalRegisters.vtimel = data;
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break;
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case 0xA:
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this->_internalRegisters.vtimeh = data;
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break;
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case 0xB:
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this->_internalRegisters.mdmaen = data;
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break;
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case 0xC:
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this->_internalRegisters.hdmaen = data;
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break;
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case 0xD:
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this->_internalRegisters.memsel = data;
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break;
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case 0x10:
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this->_internalRegisters.rdnmi = data;
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break;
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case 0x11:
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this->_internalRegisters.timeup = data;
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break;
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case 0x12:
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this->_internalRegisters.hvbjoy = data;
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break;
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case 0x13:
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this->_internalRegisters.rdio = data;
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break;
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case 0x14:
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this->_internalRegisters.rddivl = data;
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break;
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case 0x15:
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this->_internalRegisters.rddivh = data;
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break;
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case 0x16:
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this->_internalRegisters.rdmpyl = data;
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break;
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case 0x17:
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this->_internalRegisters.rdmpyh = data;
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break;
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case 0x18:
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this->_internalRegisters.joy1l = data;
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break;
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case 0x19:
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this->_internalRegisters.joy1h = data;
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break;
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case 0x1A:
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this->_internalRegisters.joy2l = data;
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break;
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case 0x1B:
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this->_internalRegisters.joy2h = data;
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break;
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case 0x1C:
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this->_internalRegisters.joy3l = data;
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break;
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case 0x1D:
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this->_internalRegisters.joy3h = data;
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break;
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case 0x1E:
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this->_internalRegisters.joy4l = data;
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break;
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case 0x1F:
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this->_internalRegisters.joy4h = data;
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break;
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default:
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throw InvalidAddress("CPU Internal Registers write", addr);
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}
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}
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unsigned CPU::update()
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{
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unsigned cycles = 0;
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for (int i = 0; i < 0xFF; i++)
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cycles += this->executeInstruction();
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return cycles;
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}
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unsigned CPU::executeInstruction()
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{
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uint8_t opcode = this->_bus->read(this->_registers.pc);
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this->_extraMemoryCycles = 0;
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switch (opcode) {
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case Instructions::BRK: return 7 + this->BRK();
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case Instructions::RTI: return 6 + this->RTI();
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case Instructions::ADC_IM: return 2 + this->ADC(this->_getImmediateAddr());
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case Instructions::ADC_ABS: return 4 + this->ADC(this->_getAbsoluteAddr());
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case Instructions::ADC_ABSl: return 5 + this->ADC(this->_getAbsoluteLongAddr());
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case Instructions::ADC_DP: return 3 + this->ADC(this->_getDirectAddr());
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case Instructions::ADC_DPi: return 5 + this->ADC(this->_getDirectIndirectAddr());
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case Instructions::ADC_DPil: return 6 + this->ADC(this->_getDirectIndirectLongAddr());
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case Instructions::ADC_ABSX: return 4 + this->ADC(this->_getAbsoluteIndexedByXAddr());
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case Instructions::ADC_ABSXl:return 5 + this->ADC(this->_getAbsoluteIndexedByXLongAddr());
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case Instructions::ADC_ABSY: return 4 + this->ADC(this->_getAbsoluteIndexedByYAddr());
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case Instructions::ADC_DPX: return 4 + this->ADC(this->_getDirectIndexedByXAddr());
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case Instructions::ADC_DPXi: return 6 + this->ADC(this->_getDirectIndirectIndexedXAddr());
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case Instructions::ADC_DPYi: return 5 + this->ADC(this->_getDirectIndirectIndexedYAddr());
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case Instructions::ADC_DPYil:return 6 + this->ADC(this->_getDirectIndirectIndexedYLongAddr());
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case Instructions::ADC_SR: return 4 + this->ADC(this->_getStackRelativeAddr());
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case Instructions::ADC_SRYi: return 7 + this->ADC(this->_getStackRelativeIndirectIndexedYAddr());
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default:
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throw InvalidOpcode("CPU", opcode);
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}
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}
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void CPU::push(uint8_t data)
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{
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this->_bus->write(this->_registers.s--, data);
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}
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void CPU::push(uint16_t data)
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{
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this->_bus->write(this->_registers.s--, data);
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this->_bus->write(this->_registers.s--, data << 8u);
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}
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uint8_t CPU::pop()
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{
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return this->_bus->read(this->_registers.s++);
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}
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uint16_t CPU::pop16()
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{
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return this->_bus->read(this->_registers.s++) + (this->_bus->read(this->_registers.s++) << 8u);
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}
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////////////////////////////////////////////////////////////////////
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/// Addressing modes
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////////////////////////////////////////////////////////////////////
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uint24_t CPU::_getImmediateAddr()
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{
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uint24_t effective = this->_registers.pac++;
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if (this->_registers.p.m)
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this->_registers.pac++;
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return effective;
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}
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uint24_t CPU::_getDirectAddr()
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{
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if (this->_registers.dl != 0)
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this->_extraMemoryCycles++;
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uint8_t addr = this->_bus->read(this->_registers.pac++);
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return this->_registers.d + addr;
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}
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uint24_t CPU::_getAbsoluteAddr()
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{
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uint24_t addr = this->_registers.dbr << 16u;
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addr += this->_bus->read(this->_registers.pac++);
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addr += this->_bus->read(this->_registers.pac++) << 8u;
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return addr;
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}
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uint24_t CPU::_getAbsoluteLongAddr()
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{
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uint24_t addr = this->_bus->read(this->_registers.pac++);
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addr += this->_bus->read(this->_registers.pac++) << 8u;
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addr += this->_bus->read(this->_registers.pac++) << 16u;
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return addr;
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}
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uint24_t CPU::_getDirectIndirectIndexedYAddr()
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{
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if (this->_registers.dl != 0)
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this->_extraMemoryCycles++;
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uint16_t dp = this->_bus->read(this->_registers.pac++) + this->_registers.d;
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uint24_t base = this->_bus->read(dp);
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base += this->_bus->read(dp + 1) << 8u;
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base += this->_registers.dbr << 16u;
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if ((base & 0xF0000000u) == (((base + this->_registers.y) & 0xF0000000u)))
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this->_extraMemoryCycles++;
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return base + this->_registers.y;
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}
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uint24_t CPU::_getDirectIndirectIndexedYLongAddr()
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{
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if (this->_registers.dl != 0)
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this->_extraMemoryCycles++;
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uint16_t dp = this->_bus->read(this->_registers.pac++) + this->_registers.d;
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uint24_t base = this->_bus->read(dp);
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base += this->_bus->read(dp + 1) << 8u;
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base += this->_bus->read(dp + 2) << 16u;
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return base;
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}
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uint24_t CPU::_getDirectIndirectIndexedXAddr()
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{
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if (this->_registers.dl != 0)
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this->_extraMemoryCycles++;
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uint16_t dp = this->_bus->read(this->_registers.pac++) + this->_registers.d;
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dp += this->_registers.x;
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uint24_t base = this->_bus->read(dp);
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base += this->_bus->read(dp + 1) << 8u;
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base += this->_registers.dbr << 16u;
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return base;
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}
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uint24_t CPU::_getDirectIndexedByXAddr()
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{
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if (this->_registers.dl != 0)
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this->_extraMemoryCycles++;
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uint16_t dp = this->_bus->read(this->_registers.pac++) + this->_registers.d;
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dp += this->_registers.x;
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return dp;
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}
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uint24_t CPU::_getDirectIndexedByYAddr()
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{
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if (this->_registers.dl != 0)
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this->_extraMemoryCycles++;
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uint16_t dp = this->_bus->read(this->_registers.pac++) + this->_registers.d;
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dp += this->_registers.y;
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return dp;
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}
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uint24_t CPU::_getAbsoluteIndexedByXAddr()
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{
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uint16_t abs = this->_bus->read(this->_registers.pac++);
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abs += this->_bus->read(this->_registers.pac++) << 8u;
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uint24_t effective = abs + (this->_registers.dbr << 16u);
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if ((effective & 0xF0000000u) == (((effective + this->_registers.x) & 0xF0000000u)))
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this->_extraMemoryCycles++;
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return effective + this->_registers.x;
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}
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uint24_t CPU::_getAbsoluteIndexedByYAddr()
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{
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uint16_t abs = this->_bus->read(this->_registers.pac++);
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abs += this->_bus->read(this->_registers.pac++) << 8u;
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uint24_t effective = abs + (this->_registers.dbr << 16u);
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if ((effective & 0xF0000000u) == (((effective + this->_registers.y) & 0xF0000000u)))
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this->_extraMemoryCycles++;
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return effective + this->_registers.y;
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}
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uint24_t CPU::_getAbsoluteIndexedByXLongAddr()
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{
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uint24_t lng = this->_bus->read(this->_registers.pac++);
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lng += this->_bus->read(this->_registers.pac++) << 8u;
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lng += this->_bus->read(this->_registers.pac++) << 16u;
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return lng + this->_registers.x;
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}
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uint24_t CPU::_getProgramCounterRelativeAddr()
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{
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uint24_t pc = this->_registers.pac;
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int8_t mod = this->_bus->read(this->_registers.pac++);
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return pc + mod;
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}
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uint24_t CPU::_getProgramCounterRelativeLongAddr()
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{
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uint24_t pc = this->_registers.pac;
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uint8_t val1 = this->_bus->read(this->_registers.pac++);
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uint8_t val2 = this->_bus->read(this->_registers.pac++);
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int16_t mod = val2 > 0x7F ? (static_cast<char>(val2) * 256 - val1) : (val1 | val2 << 8u);
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return pc + mod;
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}
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uint24_t CPU::_getAbsoluteIndirectAddr()
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{
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uint16_t abs = this->_bus->read(this->_registers.pac++);
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abs += this->_bus->read(this->_registers.pac++) << 8u;
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uint24_t effective = this->_bus->read(abs);
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effective += this->_bus->read(abs + 1) << 8u;
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return effective;
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}
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uint24_t CPU::_getAbsoluteIndexedIndirectAddr()
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{
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uint24_t abs = this->_bus->read(this->_registers.pac++);
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abs += this->_bus->read(this->_registers.pac++) << 8u;
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abs += this->_registers.x;
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uint24_t effective = this->_bus->read(abs);
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effective += this->_bus->read(abs + 1) << 8u;
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return effective;
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}
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uint24_t CPU::_getDirectIndirectAddr()
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{
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if (this->_registers.dl != 0)
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this->_extraMemoryCycles++;
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uint16_t dp = this->_bus->read(this->_registers.pac++) + this->_registers.d;
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uint24_t effective = this->_bus->read(dp);
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effective += this->_bus->read(dp + 1) << 8u;
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effective += this->_registers.dbr << 16u;
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return effective;
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}
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uint24_t CPU::_getDirectIndirectLongAddr()
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{
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if (this->_registers.dl != 0)
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this->_extraMemoryCycles++;
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uint16_t dp = this->_bus->read(this->_registers.pac++) + this->_registers.d;
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uint24_t effective = this->_bus->read(dp);
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effective += this->_bus->read(++dp) << 8u;
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effective += this->_bus->read(++dp) << 16u;
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return effective;
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}
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uint24_t CPU::_getStackRelativeAddr()
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{
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return this->_bus->read(this->_registers.pac++) + this->_registers.s;
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}
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uint24_t CPU::_getStackRelativeIndirectIndexedYAddr()
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{
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uint24_t base = this->_bus->read(this->_registers.pac++) + this->_registers.s;
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base += this->_registers.dbr << 16u;
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return base + this->_registers.y;
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}
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unsigned CPU::STA(uint24_t addr)
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{
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if (this->_registers.p.m)
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this->_bus->write(addr, this->_registers.al);
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else {
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this->_bus->write(addr, this->_registers.al);
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this->_bus->write(addr + 1, this->_registers.ah);
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}
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return 0;
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}
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} |