mirror of
https://github.com/zoriya/ComSquare.git
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226 lines
6.1 KiB
C++
226 lines
6.1 KiB
C++
//
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// Created by Melefo on 24/01/2020.
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//
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#ifndef COMSQUARE_APU_HPP
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#define COMSQUARE_APU_HPP
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#include <memory>
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#include "DSP/DSP.hpp"
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#include "../Memory/IMemory.hpp"
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#include "../Ram/Ram.hpp"
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namespace ComSquare::APU
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{
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struct InternalRegisters {
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//! @brief The X index register
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uint8_t x;
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//! @brief The YA register
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union {
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struct {
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//! @brief The Accumulator register
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uint8_t a;
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//! @brief The Y Index register
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uint8_t y;
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};
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uint16_t ya;
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};
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//! @brief The Stack pointer register
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uint8_t sp;
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//! @brief The Program counter register
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union {
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struct {
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uint8_t pcl;
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uint8_t pch;
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};
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uint16_t pc;
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};
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//! @brief Program Status Word register
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union {
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struct {
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//! @brief Negative flag
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bool n : 1;
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//! @brief Overflow flag
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bool v : 1;
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//! @brief Direct page flag
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bool p : 1;
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//! @brief Break flag
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bool b : 1;
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//! @brief Half carry flag
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bool h : 1;
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//! @brief Interrupt enabled flag
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bool i : 1;
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//! @brief Zero flag
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bool z : 1;
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//! @brief Carry flag
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bool c : 1;
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};
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uint8_t psw;
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};
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};
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struct Registers
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{
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//! @brief An undocumented register
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uint8_t unknown;
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//! @brief Control Register register
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uint8_t ctrlreg;
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//! @brief DSP Register Address register
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uint8_t dspregAddr;
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//! @brief DSP Register data register
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uint8_t dspregData;
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//! @brief Port 0 register
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uint8_t port0;
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//! @brief Port 1 register
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uint8_t port1;
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//! @brief Port 2 register
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uint8_t port2;
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//! @brief Port 3 register
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uint8_t port3;
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//! @brief Regular Memory register
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uint8_t regmem1;
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//! @brief Another Regular Memory register
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uint8_t regmem2;
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//! @brief Timer-0 register
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uint8_t timer0;
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//! @brief Timer-1 register
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uint8_t timer1;
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//! @brief Timer-2 register
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uint8_t timer2;
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//! @brief Counter-0 register
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uint8_t counter0;
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//! @brief Counter-1 register
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uint8_t counter1;
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//! @brief Counter-2 register
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uint8_t counter2;
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};
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enum StateMode
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{
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Running,
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Sleeping,
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Stopped
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};
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struct MemoryMap
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{
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//! @brief Zero page memory
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Ram::Ram Page0;
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//! @brief Stack space memory
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Ram::Ram Page1;
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//! @brief Any-use memory
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Ram::Ram Memory;
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//! @brief IPL ROM
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Ram::Ram IPL;
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MemoryMap();
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};
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class APU : public Memory::IMemory {
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private:
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//! @brief All the registers of the APU CPU
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Registers _registers{};
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//! @brief Internal registers of the CPU (accessible from the bus via addr $4200 to $421F).
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InternalRegisters _internalRegisters{};
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//! @brief Internal APU memory separated according to their utility
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MemoryMap _map;
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//! @brief The DSP component used to produce sound
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std::shared_ptr<DSP::DSP> _dsp;
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//! @brief Read from the APU ram.
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//! @param addr The address to read from. The address 0x0000 should refer to the first byte of the register.
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//! @throw InvalidAddress will be thrown if the address is more than $FFFF (the number of register).
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//! @return Return the data.
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uint8_t _internalRead(uint24_t addr);
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//! @brief Write data to the APU ram.
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//! @param addr The address to write to. The address 0x0000 should refer to the first byte of register.
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//! @param data The new value of the register.
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//! @throw InvalidAddress will be thrown if the address is more than $FFFF (the number of register).
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void _internalWrite(uint24_t addr, uint8_t data);
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//! @brief Current state of APU CPU
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StateMode _state = Running;
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//! @brief Keep the number of excess cycles executed to pad the next update
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unsigned int _paddingCycles = 0;
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//! @brief Get direct page offset
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uint24_t _getDirectAddr();
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//! @brief Get absolute direct page offset
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uint24_t _getAbsoluteAddr();
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//! @brief Execute a single instruction.
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//! @return The number of cycles that the instruction took.
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int executeInstruction();
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//! @brief No Operation instruction, do nothing than delay
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int NOP();
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//! @brief Sleep instruction, halts the processor with SLEEP mode
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int SLEEP();
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//! @brief Stop instruction, halts the processor with STOP mode
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int STOP();
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//! @brief Clear Carry instruction, set Carry flag to 0
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int CLRC();
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//! @brief Set Carry instruction, Set Carry flag to 1
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int SETC();
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//! @brief Complement Carry instruction, invert Carry flag value
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int NOTC();
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//! @brief Clear Overflow instruction, Set Overflow & Half Carry flags to 0
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int CLRV();
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//! @brief Clear Direct Page instruction, Set Direct Page flag to 0
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int CLRP();
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//! @brief Set Direct Page instruction, Set Direct Page flag to 1
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int SETP();
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//! @brief Enable interrupts instruction, Set Zero flag to 1
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int EI();
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//! @brief Disable interrupts instruction, Set Zero flag to 0
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int DI();
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//! @brief Set 1-bit instruction, set a bit in direct page
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int SET1(uint24_t dp, uint8_t bit);
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//! @brief Clear 1-bit instruction, clear a bit in direct page
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int CLR1(uint24_t dp, uint8_t bit);
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//! @brief test set 1-bit instruction, Test and set bits with absolute address
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int TSET1(uint24_t abs);
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public:
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explicit APU();
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APU(const APU &) = default;
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APU &operator=(const APU &) = default;
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~APU() = default;
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//! @brief Read from the internal APU register.
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//! @param addr The address to read from. The address 0x00 should refer to the first byte of the register.
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//! @throw InvalidAddress will be thrown if the address is more than $0F (the number of register).
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//! @return Return the value of the register.
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uint8_t read(uint24_t addr) override;
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//! @brief Write data to the internal APU register.
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//! @param addr The address to write to. The address 0x00 should refer to the first byte of register.
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//! @param data The new value of the register.
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//! @throw InvalidAddress will be thrown if the address is more than $0F (the number of register).
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void write(uint24_t addr, uint8_t data) override;
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//! @brief This function execute the instructions received until the maximum number of cycles is reached.
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//! @return The number of cycles that elapsed.
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void update(unsigned cycles);
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//! @brief This function is executed when the SNES is powered on or the reset button is pushed.
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void reset();
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};
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}
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#endif //COMSQUARE_APU_HPP
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