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a2f4ab6a17
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|---|---|---|---|
| a2f4ab6a17 | |||
| ae58943461 |
133
pcb/abyss.kicad_dru
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133
pcb/abyss.kicad_dru
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@@ -0,0 +1,133 @@
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(version 1)
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# Custom Design Rules (DRC) for KiCAD 7.0 (Stored in '<project>.kicad_dru' file).
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#
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# Matching JLCPCB capabilities: https://jlcpcb.com/capabilities/pcb-capabilities
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#
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# KiCad documentation: https://docs.kicad.org/master/id/pcbnew/pcbnew_advanced.html#custom_design_rules
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#
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# Inspiration
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# - https://gist.github.com/darkxst/f713268e5469645425eed40115fb8b49 (with comments)
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# - https://gist.github.com/denniskupec/e163d13b0a64c2044bd259f64659485e (with comments)
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# TODO new rule: NPTH pads.
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# Inner diameter of pad should be 0.4-0.5 mm larger than NPTH drill diameter.
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# JLCPCB: "We make NPTH via dry sealing film process, if customer would like a NPTH but around with pad/copper, our engineer will dig out around pad/copper about 0.2mm-0.25mm, otherwise the metal potion will be flowed into the hole and it becomes a PTH. (there will be no copper dig out optimization for single board)."
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# TODO: new rule for plated slots: min diameter/width 0.5mm
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# JLCPCB: "The minimum plated slot width is 0.5mm, which is drawn with a pad."
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# TODO new rule: non-plated slots: min diameter/width 1.0mm
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# JLCPCB: "The minimum Non-Plated Slot Width is 1.0mm, please draw the slot outline in the mechanical layer(GML or GKO)""
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(rule "Track width, outer layer (1oz copper)"
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(layer outer)
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(condition "A.Type == 'track'")
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(constraint track_width (min 0.127mm))
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)
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(rule "Track spacing, outer layer (1oz copper)"
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(layer outer)
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(condition "A.Type == 'track' && B.Type == A.Type")
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(constraint clearance (min 0.127mm))
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)
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(rule "Track width, inner layer"
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(layer inner)
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(condition "A.Type == 'track'")
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(constraint track_width (min 0.09mm))
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)
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(rule "Track spacing, inner layer"
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(layer inner)
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(condition "A.Type == 'track' && B.Type == A.Type")
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(constraint clearance (min 0.09mm))
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)
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(rule "Silkscreen text"
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(layer "?.Silkscreen")
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(condition "A.Type == 'Text' || A.Type == 'Text Box'")
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(constraint text_thickness (min 0.15mm))
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(constraint text_height (min 1mm))
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)
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(rule "Pad to Silkscreen"
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(layer outer)
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(condition "A.Type == 'pad' && B.Layer == '?.Silkscreen'")
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(constraint silk_clearance (min 0.15mm))
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)
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(rule "Edge (routed) to track clearance"
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(condition "A.Type == 'track'")
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(constraint edge_clearance (min 0.3mm))
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)
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#(rule "Edge (v-cut) to track clearance"
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# (condition "A.Type == 'track'")
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# (constraint edge_clearance (min 0.4mm))
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#)
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# JLCPCB restrictions ambiguous:
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# Illustration: 0.2 mm, 1&2 layer: 0.3 mm, multilayer: "(0.15mm more costly)"
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# This rule handles diameter minimum and maximum for ALL holes.
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# Other specialized rules handle restrictions (e.g. Via, PTH, NPTH)
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(rule "Hole diameter"
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(constraint hole_size (min 0.2mm) (max 6.3mm))
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)
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(rule "Hole (NPTH) diameter"
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(layer outer)
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(condition "!A.isPlated()")
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(constraint hole_size (min 0.5mm))
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)
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# TODO: Hole to board edge ≥ 1 mm. Min. board size 10 × 10 mm
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(rule "Hole (castellated) diameter"
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(layer outer)
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(condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'")
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(constraint hole_size (min 0.6mm))
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)
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# JLCPCB: "Via diameter should be 0.1mm(0.15mm preferred) larger than Via hole size" (illustration shows diameters for both dimensions)
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# JLCPCB: PTH: "The annular ring size will be enlarged to 0.15mm in production."
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(rule "Annular ring width (via and PTH)"
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(layer outer)
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(condition "A.isPlated()")
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(constraint annular_width (min 0.075mm))
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)
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(rule "Clearance: hole to hole (perimeter), different nets"
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(layer outer)
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(condition "A.Net != B.Net")
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(constraint hole_to_hole (min 0.5mm))
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)
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(rule "Clearance: hole to hole (perimeter), same net"
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(layer outer)
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(condition "A.Net == B.Net")
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(constraint hole_to_hole (min 0.254mm))
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)
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(rule "Clearance: track to NPTH hole (perimeter)"
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# (condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track' && A.Net != B.Net")
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(condition "!A.isPlated() && B.Type == 'track' && A.Net != B.Net")
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(constraint hole_clearance (min 0.254mm))
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)
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(rule "Clearance: track to PTH hole perimeter"
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(condition "A.isPlated() && B.Type == 'track' && A.Net != B.Net")
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(constraint hole_clearance (min 0.33mm))
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)
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# TODO: try combining with rule "Clearance: PTH to track, different nets"
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(rule "Clearance: track to pad"
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(condition "A.Type == 'pad' && B.Type == 'track' && A.Net != B.Net")
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(constraint clearance (min 0.2mm))
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)
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(rule "Clearance: pad/via to pad/via"
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(layer outer)
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# (condition "(A.Type == 'Pad' || A.Type == 'Via') && (B.Type == 'Pad' || B.Type == 'Via') && A.Net != B.Net")
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(condition "A.isPlated() && B.isPlated() && A.Net != B.Net")
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(constraint clearance (min 0.127mm))
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)
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18419
pcb/abyss.kicad_pcb
18419
pcb/abyss.kicad_pcb
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Load Diff
@@ -226,226 +226,6 @@
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"cvpcb": {
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"equivalence_files": []
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||||
},
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"erc": {
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||||
"erc_exclusions": [],
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||||
"meta": {
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||||
"version": 0
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||||
},
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||||
"pin_map": [
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[
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[
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[
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|
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|
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[
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||||
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||||
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||||
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||||
2,
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||||
2,
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||||
2,
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||||
2,
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||||
2,
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||||
2
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||||
]
|
||||
],
|
||||
"rule_severities": {
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||||
"bus_definition_conflict": "error",
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||||
"bus_entry_needed": "error",
|
||||
"bus_to_bus_conflict": "error",
|
||||
"bus_to_net_conflict": "error",
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||||
"different_unit_footprint": "error",
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||||
"different_unit_net": "error",
|
||||
"duplicate_reference": "error",
|
||||
"duplicate_sheet_names": "error",
|
||||
"endpoint_off_grid": "warning",
|
||||
"extra_units": "error",
|
||||
"footprint_filter": "ignore",
|
||||
"footprint_link_issues": "warning",
|
||||
"four_way_junction": "ignore",
|
||||
"global_label_dangling": "warning",
|
||||
"hier_label_mismatch": "error",
|
||||
"label_dangling": "error",
|
||||
"label_multiple_wires": "warning",
|
||||
"lib_symbol_issues": "warning",
|
||||
"lib_symbol_mismatch": "warning",
|
||||
"missing_bidi_pin": "warning",
|
||||
"missing_input_pin": "warning",
|
||||
"missing_power_pin": "error",
|
||||
"missing_unit": "warning",
|
||||
"multiple_net_names": "warning",
|
||||
"net_not_bus_member": "warning",
|
||||
"no_connect_connected": "warning",
|
||||
"no_connect_dangling": "warning",
|
||||
"pin_not_connected": "error",
|
||||
"pin_not_driven": "error",
|
||||
"pin_to_pin": "warning",
|
||||
"power_pin_not_driven": "error",
|
||||
"same_local_global_label": "warning",
|
||||
"similar_label_and_power": "warning",
|
||||
"similar_labels": "warning",
|
||||
"similar_power": "warning",
|
||||
"simulation_model_issue": "ignore",
|
||||
"single_global_label": "ignore",
|
||||
"unannotated": "error",
|
||||
"unconnected_wire_endpoint": "warning",
|
||||
"unit_value_mismatch": "error",
|
||||
"unresolved_variable": "error",
|
||||
"wire_dangling": "error"
|
||||
}
|
||||
},
|
||||
"libraries": {
|
||||
"pinned_footprint_libs": [],
|
||||
"pinned_symbol_libs": []
|
||||
@@ -615,124 +395,15 @@
|
||||
"plot": "",
|
||||
"pos_files": "",
|
||||
"specctra_dsn": "",
|
||||
"step": "",
|
||||
"step": "abyss.stl",
|
||||
"svg": "",
|
||||
"vrml": ""
|
||||
},
|
||||
"page_layout_descr_file": ""
|
||||
},
|
||||
"schematic": {
|
||||
"annotate_start_num": 0,
|
||||
"bom_export_filename": "${PROJECTNAME}.csv",
|
||||
"bom_fmt_presets": [],
|
||||
"bom_fmt_settings": {
|
||||
"field_delimiter": ",",
|
||||
"keep_line_breaks": false,
|
||||
"keep_tabs": false,
|
||||
"name": "CSV",
|
||||
"ref_delimiter": ",",
|
||||
"ref_range_delimiter": "",
|
||||
"string_delimiter": "\""
|
||||
},
|
||||
"bom_presets": [],
|
||||
"bom_settings": {
|
||||
"exclude_dnp": false,
|
||||
"fields_ordered": [
|
||||
{
|
||||
"group_by": false,
|
||||
"label": "Reference",
|
||||
"name": "Reference",
|
||||
"show": true
|
||||
},
|
||||
{
|
||||
"group_by": false,
|
||||
"label": "Qty",
|
||||
"name": "${QUANTITY}",
|
||||
"show": true
|
||||
},
|
||||
{
|
||||
"group_by": true,
|
||||
"label": "Value",
|
||||
"name": "Value",
|
||||
"show": true
|
||||
},
|
||||
{
|
||||
"group_by": true,
|
||||
"label": "DNP",
|
||||
"name": "${DNP}",
|
||||
"show": true
|
||||
},
|
||||
{
|
||||
"group_by": true,
|
||||
"label": "Exclude from BOM",
|
||||
"name": "${EXCLUDE_FROM_BOM}",
|
||||
"show": true
|
||||
},
|
||||
{
|
||||
"group_by": true,
|
||||
"label": "Exclude from Board",
|
||||
"name": "${EXCLUDE_FROM_BOARD}",
|
||||
"show": true
|
||||
},
|
||||
{
|
||||
"group_by": true,
|
||||
"label": "Footprint",
|
||||
"name": "Footprint",
|
||||
"show": true
|
||||
},
|
||||
{
|
||||
"group_by": false,
|
||||
"label": "Datasheet",
|
||||
"name": "Datasheet",
|
||||
"show": true
|
||||
}
|
||||
],
|
||||
"filter_string": "",
|
||||
"group_symbols": true,
|
||||
"include_excluded_from_bom": true,
|
||||
"name": "Default Editing",
|
||||
"sort_asc": true,
|
||||
"sort_field": "Reference"
|
||||
},
|
||||
"connection_grid_size": 50.0,
|
||||
"drawing": {
|
||||
"dashed_lines_dash_length_ratio": 12.0,
|
||||
"dashed_lines_gap_length_ratio": 3.0,
|
||||
"default_line_thickness": 6.0,
|
||||
"default_text_size": 50.0,
|
||||
"field_names": [],
|
||||
"intersheets_ref_own_page": false,
|
||||
"intersheets_ref_prefix": "",
|
||||
"intersheets_ref_short": false,
|
||||
"intersheets_ref_show": false,
|
||||
"intersheets_ref_suffix": "",
|
||||
"junction_size_choice": 3,
|
||||
"label_size_ratio": 0.375,
|
||||
"operating_point_overlay_i_precision": 3,
|
||||
"operating_point_overlay_i_range": "~A",
|
||||
"operating_point_overlay_v_precision": 3,
|
||||
"operating_point_overlay_v_range": "~V",
|
||||
"overbar_offset_ratio": 1.23,
|
||||
"pin_symbol_size": 25.0,
|
||||
"text_offset_ratio": 0.15
|
||||
},
|
||||
"legacy_lib_dir": "",
|
||||
"legacy_lib_list": [],
|
||||
"meta": {
|
||||
"version": 1
|
||||
},
|
||||
"net_format_name": "",
|
||||
"page_layout_descr_file": "",
|
||||
"plot_directory": "",
|
||||
"space_save_all_events": true,
|
||||
"spice_current_sheet_as_root": false,
|
||||
"spice_external_command": "spice \"%I\"",
|
||||
"spice_model_current_sheet_as_root": true,
|
||||
"spice_save_all_currents": false,
|
||||
"spice_save_all_dissipations": false,
|
||||
"spice_save_all_voltages": false,
|
||||
"subpart_first_id": 65,
|
||||
"subpart_id_separator": 0
|
||||
"legacy_lib_list": []
|
||||
},
|
||||
"sheets": [],
|
||||
"text_variables": {}
|
||||
|
||||
Reference in New Issue
Block a user