Merging master

sources/CPU/CPU.cpp

@@ -54,7 +54,7 @@ namespace ComSquare::CPU
 		case 0xA:
 			return this->_internalRegisters.vtimeh;
 		case 0xB:
-			return this->_internalRegisters.mdmaen;
+			return this->_internalRegisters.dmaEnableRegister;
 		case 0xC:
 			return this->_internalRegisters.hdmaen;
 		case 0xD:
@@ -209,8 +209,14 @@ namespace ComSquare::CPU
 	unsigned CPU::update()
 	{
 		unsigned cycles = 0;
+		const unsigned maxCycles = 0x17;
 
-		for (int i = 0; i < 0x17; i++) {
+		for (int i = 0; i < 8; i++) {
+			if (!(this->_internalRegisters.dmaEnableRegister & (0xF << i)))
+				continue;
+			cycles += this->_dmaChannels[i].run(maxCycles - cycles);
+		}
+		for (unsigned i = 0; i < maxCycles; i++) {
 			if (this->_isStopped) {
 				cycles += 1;
 				continue;

sources/CPU/CPU.hpp

@@ -132,7 +132,7 @@ namespace ComSquare::CPU
 		uint8_t vtimeh;
 
 		//! @brief DMA Enable Register
-		uint8_t mdmaen;
+		uint8_t dmaEnableRegister;
 
 		//! @brief HDMA Enable Register
 		uint8_t hdmaen;

sources/CPU/DMA/DMA.cpp

@@ -56,4 +56,9 @@ namespace ComSquare::CPU
 			throw InvalidAddress("DMA read", addr);
 		}
 	}
+
+	uint8_t DMA::run(unsigned int cycles)
+	{
+		return 0;
+	}
 }

sources/CPU/DMA/DMA.hpp

@@ -61,6 +61,11 @@ namespace ComSquare::CPU
 		//! @brief Bus helper to write to this channel.
 		void write(uint8_t addr, uint8_t data);
 
+		//! @brief Run the DMA for x cycles
+		//! @param cycles The maximum number of cycles this DMA should run.
+		//! @return the number of cycles taken
+		uint8_t run(unsigned cycles);
+
 		DMA() = default;
 		DMA(const DMA &) = default;
 		DMA &operator=(const DMA &) = default;