Creating the DMA class

CMakeLists.txt

@@ -99,7 +99,7 @@ add_executable(unit_tests
         tests/testRectangleMemory.cpp
         tests/CPU/Math/testCMP.cpp
         sources/PPU/Backgrounds.cpp
-        sources/PPU/Background.cpp sources/PPU/Background.hpp)
+        sources/PPU/Background.cpp sources/PPU/Background.hpp sources/CPU/DMA/DMA.cpp sources/CPU/DMA/DMA.hpp)
 
 # include criterion & coverage
 target_link_libraries(unit_tests criterion -lgcov)
@@ -215,7 +215,7 @@ add_executable(ComSquare
         sources/Debugger/CGramDebug.hpp
         sources/Models/Vector2.hpp
         sources/PPU/Backgrounds.cpp
-        sources/PPU/Background.cpp sources/PPU/Background.hpp)
+        sources/PPU/Background.cpp sources/PPU/Background.hpp sources/CPU/DMA/DMA.cpp sources/CPU/DMA/DMA.hpp)
 
 target_compile_definitions(ComSquare PUBLIC DEBUGGER_ENABLED)
 

sources/CPU/DMA/DMA.cpp

@@ -0,0 +1,5 @@
+//
+// Created by anonymus-raccoon on 5/26/20.
+//
+
+#include "DMA.hpp"

sources/CPU/DMA/DMA.hpp

@@ -0,0 +1,60 @@
+//
+// Created by anonymus-raccoon on 5/26/20.
+//
+
+#ifndef COMSQUARE_DMA_HPP
+#define COMSQUARE_DMA_HPP
+
+#include <cstdint>
+#include "../../Models/Int24.hpp"
+
+namespace ComSquare::CPU
+{
+	//! @brief The first three bytes of the DMA's control register. Used to tell how many bytes/registers there is.
+	enum DMAMode {
+		//! @brief 1 byte is transferred to 1 register (write once)
+		OneToOne = 0b000,
+		//! @brief 2 byte is transferred to 2 register (write once)
+		TwoToTwo = 0b001,
+		//! @brief 2 byte is transferred to 1 register (write twice)
+		TwoToOne = 0b010,
+		//! @brief 4 byte is transferred to 2 register (write twice)
+		FourToTwo = 0b011,
+		//! @brief 4 byte is transferred to 4 register (write once)
+		FourToFour = 0b100
+	};
+
+	//! @brief Class handling all DMA/HDMA transfers (Direct Memory Access or H-Blank Direct Memory Access)
+	class DMA {
+	public:
+		//! @brief DMA Control register (various information about the transfer)
+		union {
+			struct {
+				//! @brief The direction of the transfer (0: CPU to PPU aka A to B, 1: PPU to CPU aka B to A).
+				bool direction: 1;
+				//! @brief Two unused bites.
+				bool _: 2;
+				//! @brief if this flag is 0: increment. Else: decrement. (The A address)
+				bool increment: 1;
+				//! @brief If this flag is set, no increment/decrement will be done.
+				bool fixed: 1;
+				//! @brief DMA's mode: how many bytes/registers there is, how many writes...
+				enum DMAMode mode: 3;
+			};
+			uint8_t raw;
+		} controlRegister;
+		//! @brief If this is 'xx', the register accessed will be $21xx.
+		uint8_t port;
+		//! @brief The absolute long address of the data from the A bus.
+		uint24_t aAddress;
+		//! @brief The number of bytes to be transferred.
+		uint16_t count;
+
+		DMA() = default;
+		DMA(DMA &) = default;
+		DMA &operator=(DMA &) = default;
+		~DMA() = default;
+	};
+}
+
+#endif //COMSQUARE_DMA_HPP

sources/Memory/MemoryBus.cpp

@@ -22,12 +22,13 @@ namespace ComSquare::Memory
 		return *it;
 	}
 
-	uint8_t MemoryBus::read(uint24_t addr, bool)
+	uint8_t MemoryBus::read(uint24_t addr, bool silence)
 	{
 		std::shared_ptr<AMemory> handler = this->getAccessor(addr);
 
 		if (!handler) {
-			std::cout << "Unknown memory accessor for address " << std::hex << addr << ". Using open bus." << std::endl;
+			if (!silence)
+				std::cout << "Unknown memory accessor for address $" << std::hex << addr << ". Using open bus." << std::endl;
 			return this->_openBus;
 		}
 		uint8_t data =  handler->read(addr - handler->getStart());