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Fixing APU read & write

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This commit is contained in:
Melefo
2020-02-07 14:08:00 +01:00
parent 69d1cb9197
commit 9288bf3829
2 changed files with 12 additions and 56 deletions
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sources/APU/APU.cpp
+8 -51
View File
@@ -14,30 +14,14 @@ namespace ComSquare::APU
uint8_t APU::read(uint24_t addr)
{
switch (addr) {
case 0xF0:
return this->_registers.unknown;
case 0xF2:
return this->_registers.dspregAddr;
case 0xF3:
return this->_registers.dspregData;
case 0xF4:
case 0x00:
return this->_registers.port0;
case 0xF5:
case 0x01:
return this->_registers.port1;
case 0xF6:
case 0x02:
return this->_registers.port2;
case 0xF7:
case 0x03:
return this->_registers.port3;
case 0xF8:
return this->_registers.regmem1;
case 0xF9:
return this->_registers.regmem2;
case 0xFD:
return this->_registers.counter0;
case 0xFE:
return this->_registers.counter1;
case 0xFF:
return this->_registers.counter2;
default:
throw InvalidAddress("APU Registers read", addr);
}
@@ -46,45 +30,18 @@ namespace ComSquare::APU
void APU::write(uint24_t addr, uint8_t data)
{
switch (addr) {
case 0xF0:
this->_registers.unknown = data;
break;
case 0xF1:
this->_registers.ctrlreg = data;
break;
case 0xF2:
this->_registers.dspregAddr = data;
break;
case 0xF3:
this->_registers.dspregData = data;
break;
case 0xF4:
case 0x00:
this->_registers.port0 = data;
break;
case 0xF5:
case 0x01:
this->_registers.port1 = data;
break;
case 0xF6:
case 0x02:
this->_registers.port2 = data;
break;
case 0xF7:
case 0x03:
this->_registers.port3 = data;
break;
case 0xF8:
this->_registers.regmem1 = data;
break;
case 0xF9:
this->_registers.regmem2 = data;
break;
case 0xFA:
this->_registers.timer0 = data;
break;
case 0xFB:
this->_registers.timer1 = data;
break;
case 0xFC:
this->_registers.timer2 = data;
break;
default:
throw InvalidAddress("APU Registers write", addr);
}
tests/testMemoryBus.cpp
+4 -5
View File
@@ -3,6 +3,7 @@
//
#include <criterion/criterion.h>
#include <criterion/redirect.h>
#include <iostream>
#include "communism.hpp"
#include "../sources/Memory/MemoryBus.hpp"
@@ -26,8 +27,6 @@ std::pair<Memory::MemoryBus, SNES> Init()
snes.cartridge->header.mappingMode = Cartridge::LoRom;
snes.sram->_size = 10;
snes.sram->_data = new uint8_t[snes.cartridge->_size];
snes.wram->_size = 10;
snes.wram->_data = new uint8_t[snes.cartridge->_size];
bus.mapComponents(snes);
return std::make_pair(bus, snes);
}
@@ -251,7 +250,7 @@ Test(BusAccessor, GetRomMirror3)
// //
///////////////////////////
Test(BusRead, ReadOutside)
Test(BusRead, ReadOutside, .init = cr_redirect_stdout)
{
auto pair = Init();
uint8_t data;
@@ -261,7 +260,7 @@ Test(BusRead, ReadOutside)
cr_assert_eq(data, 123);
}
Test(BusRead, ReadOutside2)
Test(BusRead, ReadOutside2, .init = cr_redirect_stdout)
{
auto pair = Init();
uint8_t data;
@@ -271,7 +270,7 @@ Test(BusRead, ReadOutside2)
cr_assert_eq(data, 123);
}
Test(BusRead, ReadOutside3)
Test(BusRead, ReadOutside3, .init = cr_redirect_stdout)
{
auto pair = Init();
uint8_t data;