Anonymus Raccoon
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b29d1c4216
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Implementing TRB
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2020-05-13 17:04:14 +02:00 |
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Anonymus Raccoon
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4c4cc6b655
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Implementing ROR
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2020-05-13 16:35:13 +02:00 |
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Anonymus Raccoon
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deab98dac0
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Implementing ROL
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2020-05-13 14:58:37 +02:00 |
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Anonymus Raccoon
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475986580d
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Implementing LSR
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2020-05-13 14:39:46 +02:00 |
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Anonymus Raccoon
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66f82dc5f0
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Implementing ASL
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2020-05-13 14:11:58 +02:00 |
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Anonymus Raccoon
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abe445d202
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Adding the BIT instruction
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2020-04-28 23:12:43 +02:00 |
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Anonymus Raccoon
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b9ff47584e
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Finishing the TSB
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2020-04-08 11:39:43 +02:00 |
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Anonymus Raccoon
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5485534006
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Adding TSB
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2020-04-08 11:17:47 +02:00 |
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Anonymus Raccoon
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724a2ca616
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Implementing the AND
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2020-04-06 17:29:06 +02:00 |
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Anonymus Raccoon
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9be49e283d
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Solving timing issues
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2020-03-28 20:47:13 +01:00 |
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Anonymus Raccoon
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bd948b520c
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Implementing an array of instructions with method's pointer for the CPU (it does not work well for now
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2020-03-26 03:39:55 +01:00 |
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Anonymus Raccoon
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6c3c832539
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Solving mistakes about the m flag
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2020-02-28 00:37:17 +01:00 |
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AnonymusRaccoon
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91150dfbc1
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Adding the AND instruction
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2020-02-20 18:32:21 +01:00 |
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