ComSquare
CPU.hpp
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1 //
2 // Created by anonymus-raccoon on 1/24/20.
3 //
4 
5 #pragma once
6 
7 
8 #include "Memory/AMemory.hpp"
9 #include "Memory/MemoryBus.hpp"
10 #include "Models/Ints.hpp"
11 #include "Models/Callback.hpp"
12 #include "Cartridge/Cartridge.hpp"
13 #include "Memory/AMemory.hpp"
14 #include "Instruction.hpp"
15 #include "DMA/DMA.hpp"
16 #include "CPU/Registers.hpp"
17 
18 #ifdef DEBUGGER_ENABLED
19 #include "Debugger/CPU/CPUDebug.hpp"
20 #include "Debugger/RegisterViewer.hpp"
21 #endif
22 
23 namespace ComSquare::CPU
24 {
26  class CPU : public Memory::AMemory
27  {
28  private:
30  Registers _registers {};
32  InternalRegisters _internalRegisters {};
33 
35  bool _isEmulationMode = true;
37  bool _isStopped = false;
39  bool _isWaitingForInterrupt = false;
40 
42  std::reference_wrapper<Memory::IMemoryBus> _bus;
44  Cartridge::Header &_cartridgeHeader;
45 
47  std::array<DMA, 8> _dmaChannels;
48 
50  bool _hasIndexCrossedPageBoundary = false;
51 
53  uint24_t _getImmediateAddr8Bits();
55  uint24_t _getImmediateAddr16Bits();
57  uint24_t _getImmediateAddrForA();
59  uint24_t _getImmediateAddrForX();
61  uint24_t _getDirectAddr();
63  uint24_t _getAbsoluteAddr();
65  uint24_t _getAbsoluteLongAddr();
67  uint24_t _getDirectIndirectIndexedYAddr();
69  uint24_t _getDirectIndirectIndexedYLongAddr();
71  uint24_t _getDirectIndirectIndexedXAddr();
73  uint24_t _getDirectIndexedByXAddr();
75  uint24_t _getDirectIndexedByYAddr();
77  uint24_t _getAbsoluteIndexedByXAddr();
79  uint24_t _getAbsoluteIndexedByYAddr();
81  uint24_t _getAbsoluteIndexedByXLongAddr();
83  uint24_t _getAbsoluteIndirectAddr();
85  uint24_t _getAbsoluteIndirectLongAddr();
87  uint24_t _getAbsoluteIndirectIndexedByXAddr();
89  uint24_t _getDirectIndirectAddr();
91  uint24_t _getDirectIndirectLongAddr();
93  uint24_t _getStackRelativeAddr();
95  uint24_t _getStackRelativeIndirectIndexedYAddr();
96 
98  void _push(uint8_t data);
100  void _push(uint16_t data);
102  uint8_t _pop();
104  uint16_t _pop16();
105 
107  inline uint8_t _readPC()
108  {
109  uint8_t ret = this->getBus().read(this->_registers.pac);
110  this->_registers.pc++;
111  return ret;
112  }
113 
115  void _checkInterrupts();
117  void _runInterrupt(uint24_t nativeHandler, uint24_t emulationHandler);
118 
122  uint24_t _getValueAddr(const Instruction &instruction);
123 
125  int BRK(uint24_t, AddressingMode);
127  int COP(uint24_t, AddressingMode);
129  int RTI(uint24_t, AddressingMode);
131  int ADC(uint24_t valueAddr, AddressingMode);
133  int STA(uint24_t addr, AddressingMode);
135  int STX(uint24_t addr, AddressingMode);
137  int STY(uint24_t addr, AddressingMode);
139  int STZ(uint24_t addr, AddressingMode);
141  int LDA(uint24_t addr, AddressingMode);
143  int LDX(uint24_t addr, AddressingMode);
145  int LDY(uint24_t addr, AddressingMode);
147  int SEP(uint24_t valueAddr, AddressingMode);
149  int REP(uint24_t valueAddr, AddressingMode);
151  int JSR(uint24_t addr, AddressingMode);
153  int JSL(uint24_t addr, AddressingMode);
155  int PHA(uint24_t, AddressingMode);
157  int PHB(uint24_t, AddressingMode);
159  int PHD(uint24_t, AddressingMode);
161  int PHK(uint24_t, AddressingMode);
163  int PHP(uint24_t, AddressingMode);
165  int PHX(uint24_t, AddressingMode);
167  int PHY(uint24_t, AddressingMode);
169  int PLA(uint24_t, AddressingMode);
171  int PLB(uint24_t, AddressingMode);
173  int PLD(uint24_t, AddressingMode);
175  int PLP(uint24_t, AddressingMode);
177  int PLX(uint24_t, AddressingMode);
179  int PLY(uint24_t, AddressingMode);
181  int CLC(uint24_t, AddressingMode);
183  int CLI(uint24_t, AddressingMode);
185  int CLD(uint24_t, AddressingMode);
187  int CLV(uint24_t, AddressingMode);
189  int SEC(uint24_t, AddressingMode);
191  int SED(uint24_t, AddressingMode);
193  int SEI(uint24_t, AddressingMode);
195  int XCE(uint24_t, AddressingMode);
197  int AND(uint24_t valueAddr, AddressingMode);
199  int SBC(uint24_t valueAddr, AddressingMode);
201  int TAX(uint24_t, AddressingMode);
203  int TAY(uint24_t, AddressingMode);
205  int TXS(uint24_t, AddressingMode);
207  int INX(uint24_t, AddressingMode);
209  int INY(uint24_t, AddressingMode);
211  int CPX(uint24_t valueAddr, AddressingMode);
213  int CPY(uint24_t valueAddr, AddressingMode);
215  int BCC(uint24_t valueAddr, AddressingMode);
217  int BCS(uint24_t valueAddr, AddressingMode);
219  int BEQ(uint24_t valueAddr, AddressingMode);
221  int BNE(uint24_t valueAddr, AddressingMode);
223  int BMI(uint24_t valueAddr, AddressingMode);
225  int BPL(uint24_t valueAddr, AddressingMode);
227  int BVC(uint24_t valueAddr, AddressingMode);
229  int BVS(uint24_t valueAddr, AddressingMode);
231  int BRA(uint24_t valueAddr, AddressingMode);
233  int BRL(uint24_t valueAddr, AddressingMode);
235  int JMP(uint24_t valueAddr, AddressingMode);
237  int JML(uint24_t valueAddr, AddressingMode);
239  int NOP(uint24_t, AddressingMode);
241  int DEX(uint24_t, AddressingMode);
243  int DEY(uint24_t, AddressingMode);
245  int ORA(uint24_t valueAddr, AddressingMode mode);
247  int RTS(uint24_t, AddressingMode);
249  int RTL(uint24_t, AddressingMode);
251  int CMP(uint24_t, AddressingMode);
253  int INC(uint24_t, AddressingMode);
255  int DEC(uint24_t, AddressingMode);
257  int EOR(uint24_t, AddressingMode);
259  int TCD(uint24_t, AddressingMode);
261  int TCS(uint24_t, AddressingMode);
263  int TDC(uint24_t, AddressingMode);
265  int TSC(uint24_t, AddressingMode);
267  int TSX(uint24_t, AddressingMode);
269  int TXA(uint24_t, AddressingMode);
271  int TYA(uint24_t, AddressingMode);
273  int TXY(uint24_t, AddressingMode);
275  int TYX(uint24_t, AddressingMode);
277  int TSB(uint24_t, AddressingMode);
279  int TRB(uint24_t, AddressingMode);
281  int XBA(uint24_t, AddressingMode);
283  int BIT(uint24_t, AddressingMode);
285  int ASL(uint24_t, AddressingMode);
286  // !@brief Logical Shift Right
287  int LSR(uint24_t, AddressingMode);
288  // !@brief Rotate Left
289  int ROL(uint24_t, AddressingMode);
290  // !@brief Rotate Right
291  int ROR(uint24_t, AddressingMode);
293  int PER(uint24_t, AddressingMode);
295  int PEI(uint24_t, AddressingMode);
297  int PEA(uint24_t, AddressingMode);
299  int STP(uint24_t, AddressingMode);
301  int WAI(uint24_t, AddressingMode);
303  int WDM(uint24_t, AddressingMode);
308  int MVN(uint24_t, AddressingMode);
313  int MVP(uint24_t, AddressingMode);
314 
315  public:
317  [[nodiscard]] inline Memory::IMemoryBus &getBus()
318  {
319  return this->_bus;
320  }
323  void setBus(Memory::IMemoryBus &bus);
324 
327  const Instruction instructions[0x100] = {
328  {&CPU::BRK, 7, "brk", AddressingMode::Immediate8bits, 2}, // 00
329  {&CPU::ORA, 6, "ora", AddressingMode::DirectPageIndirectIndexedByX, 2}, // 01
330  {&CPU::COP, 7, "cop", AddressingMode::Immediate8bits, 2}, // 02
331  {&CPU::ORA, 4, "ora", AddressingMode::StackRelative, 2}, // 03
332  {&CPU::TSB, 5, "tsb", AddressingMode::DirectPage, 2}, // 04
333  {&CPU::ORA, 3, "ora", AddressingMode::DirectPage, 2}, // 05
334  {&CPU::ASL, 5, "asl", AddressingMode::DirectPage, 2}, // 06
335  {&CPU::ORA, 6, "ora", AddressingMode::DirectPageIndirectLong, 2}, // 07
336  {&CPU::PHP, 3, "php", AddressingMode::Implied, 1}, // 08
337  {&CPU::ORA, 2, "ora", AddressingMode::ImmediateForA, 2}, // 09
338  {&CPU::ASL, 2, "asl", AddressingMode::Implied, 1}, // 0A
339  {&CPU::PHD, 4, "phd", AddressingMode::Implied, 1}, // 0B
340  {&CPU::TSB, 6, "tsb", AddressingMode::Absolute, 3}, // 0C
341  {&CPU::ORA, 3, "ora", AddressingMode::Absolute, 4}, // 0D
342  {&CPU::ASL, 6, "asl", AddressingMode::Absolute, 3}, // 0E
343  {&CPU::ORA, 5, "ora", AddressingMode::AbsoluteLong, 5}, // 0F
344  {&CPU::BPL, 7, "bpl", AddressingMode::Immediate8bits, 2}, // 10
345  {&CPU::ORA, 5, "ora", AddressingMode::DirectPageIndirectIndexedByY, 2}, // 11
346  {&CPU::ORA, 5, "ora", AddressingMode::DirectPageIndirect, 2}, // 12
347  {&CPU::ORA, 7, "ora", AddressingMode::StackRelativeIndirectIndexedByY, 2}, // 13
348  {&CPU::TRB, 5, "trb", AddressingMode::DirectPage, 2}, // 14
349  {&CPU::ORA, 4, "ora", AddressingMode::DirectPageIndexedByX, 2}, // 15
350  {&CPU::ASL, 6, "asl", AddressingMode::DirectPageIndexedByX, 2}, // 16
351  {&CPU::ORA, 6, "ora", AddressingMode::DirectPageIndirectIndexedByYLong, 2}, // 17
352  {&CPU::CLC, 2, "clc", AddressingMode::Implied, 1}, // 18
353  {&CPU::ORA, 4, "ora", AddressingMode::AbsoluteIndexedByY, 3}, // 19
354  {&CPU::INC, 2, "inc", AddressingMode::Implied, 1}, // 1A
355  {&CPU::TCS, 2, "tcs", AddressingMode::Implied, 1}, // 1B
356  {&CPU::TRB, 6, "trb", AddressingMode::Absolute, 3}, // 1C
357  {&CPU::ORA, 4, "ora", AddressingMode::AbsoluteIndexedByX, 3}, // 1D
358  {&CPU::ASL, 7, "asl", AddressingMode::AbsoluteIndexedByX, 3}, // 1E
359  {&CPU::ORA, 5, "ora", AddressingMode::AbsoluteIndexedByXLong, 4}, // 1F
360  {&CPU::JSR, 6, "jsr", AddressingMode::Absolute, 3}, // 20
361  {&CPU::AND, 6, "and", AddressingMode::DirectPageIndirectIndexedByX, 2}, // 21
362  {&CPU::JSL, 8, "jsl", AddressingMode::AbsoluteLong, 4}, // 22
363  {&CPU::AND, 4, "and", AddressingMode::StackRelative, 2}, // 23
364  {&CPU::BIT, 3, "bit", AddressingMode::DirectPage, 2}, // 24
365  {&CPU::AND, 3, "and", AddressingMode::DirectPage, 2}, // 25
366  {&CPU::ROL, 5, "rol", AddressingMode::DirectPage, 2}, // 26
367  {&CPU::AND, 6, "and", AddressingMode::DirectPageIndirectLong, 2}, // 27
368  {&CPU::PLP, 4, "plp", AddressingMode::Implied, 1}, // 28
369  {&CPU::AND, 2, "and", AddressingMode::ImmediateForA, 2}, // 29
370  {&CPU::ROL, 2, "rol", AddressingMode::Implied, 1}, // 2A
371  {&CPU::PLD, 5, "pld", AddressingMode::Implied, 1}, // 2B
372  {&CPU::BIT, 4, "bit", AddressingMode::Absolute, 3}, // 2C
373  {&CPU::AND, 4, "and", AddressingMode::Absolute, 3}, // 2D
374  {&CPU::ROL, 6, "rol", AddressingMode::Absolute, 3}, // 2E
375  {&CPU::AND, 5, "and", AddressingMode::AbsoluteLong, 4}, // 2F
376  {&CPU::BMI, 2, "bmi", AddressingMode::Immediate8bits, 2}, // 30
377  {&CPU::AND, 5, "and", AddressingMode::DirectPageIndirectIndexedByY, 2}, // 31
378  {&CPU::AND, 5, "and", AddressingMode::DirectPageIndirect, 2}, // 32
379  {&CPU::AND, 7, "and", AddressingMode::StackRelativeIndirectIndexedByY, 2}, // 33
380  {&CPU::BIT, 4, "bit", AddressingMode::DirectPageIndexedByX, 2}, // 34
381  {&CPU::AND, 4, "and", AddressingMode::DirectPageIndexedByX, 2}, // 35
382  {&CPU::ROL, 6, "rol", AddressingMode::DirectPageIndexedByX, 2}, // 36
383  {&CPU::AND, 6, "and", AddressingMode::DirectPageIndirectIndexedByYLong, 2}, // 37
384  {&CPU::SEC, 2, "sec", AddressingMode::Implied, 1}, // 38
385  {&CPU::AND, 4, "and", AddressingMode::AbsoluteIndexedByY, 3}, // 39
386  {&CPU::DEC, 2, "dec", AddressingMode::Implied, 1}, // 3A
387  {&CPU::TSC, 2, "tsc", AddressingMode::Implied, 1}, // 3B
388  {&CPU::BIT, 4, "bit", AddressingMode::AbsoluteIndexedByX, 3}, // 3C
389  {&CPU::AND, 4, "and", AddressingMode::AbsoluteIndexedByX, 3}, // 3D
390  {&CPU::ROL, 7, "rol", AddressingMode::AbsoluteIndexedByX, 3}, // 3E
391  {&CPU::AND, 5, "and", AddressingMode::AbsoluteIndexedByXLong, 4}, // 3F
392  {&CPU::RTI, 6, "rti", AddressingMode::Implied, 1}, // 40
393  {&CPU::EOR, 6, "eor", AddressingMode::DirectPageIndirectIndexedByX, 2}, // 41
394  {&CPU::WDM, 2, "wdm", AddressingMode::Immediate8bits, 2}, // 42
395  {&CPU::EOR, 4, "eor", AddressingMode::StackRelative, 2}, // 43
396  {&CPU::MVP, 0, "mvp", AddressingMode::Immediate16bits, 3}, // 44
397  {&CPU::EOR, 3, "eor", AddressingMode::DirectPage, 2}, // 45
398  {&CPU::LSR, 5, "lsr", AddressingMode::DirectPage, 2}, // 46
399  {&CPU::EOR, 6, "eor", AddressingMode::DirectPageIndirectLong, 2}, // 47
400  {&CPU::PHA, 3, "pha", AddressingMode::Implied, 1}, // 48
401  {&CPU::EOR, 2, "eor", AddressingMode::ImmediateForA, 2}, // 49
402  {&CPU::LSR, 2, "lsr", AddressingMode::Implied, 1}, // 4A
403  {&CPU::PHK, 3, "phk", AddressingMode::Implied, 1}, // 4B
404  {&CPU::JMP, 3, "jmp", AddressingMode::Absolute, 3}, // 4C
405  {&CPU::EOR, 4, "eor", AddressingMode::Absolute, 3}, // 4D
406  {&CPU::LSR, 6, "lsr", AddressingMode::Absolute, 3}, // 4E
407  {&CPU::EOR, 5, "eor", AddressingMode::AbsoluteLong, 4}, // 4F
408  {&CPU::BVC, 2, "bvc", AddressingMode::Immediate8bits, 2}, // 50
409  {&CPU::EOR, 5, "eor", AddressingMode::DirectPageIndirectIndexedByY, 2}, // 51
410  {&CPU::EOR, 5, "eor", AddressingMode::DirectPageIndirect, 2}, // 52
411  {&CPU::EOR, 4, "eor", AddressingMode::StackRelativeIndirectIndexedByY, 2}, // 53
412  {&CPU::MVN, 0, "mvn", AddressingMode::Immediate16bits, 2}, // 54
413  {&CPU::EOR, 4, "eor", AddressingMode::DirectPageIndexedByX, 2}, // 55
414  {&CPU::LSR, 6, "lsr", AddressingMode::DirectPageIndexedByX, 2}, // 56
415  {&CPU::EOR, 6, "eor", AddressingMode::DirectPageIndirectIndexedByYLong, 2}, // 57
416  {&CPU::CLI, 2, "cli", AddressingMode::Implied, 1}, // 58
417  {&CPU::EOR, 4, "eor", AddressingMode::AbsoluteIndexedByY, 3}, // 59
418  {&CPU::PHY, 3, "phy", AddressingMode::Implied, 1}, // 5A
419  {&CPU::TCD, 2, "tcd", AddressingMode::Implied, 1}, // 5B
420  {&CPU::JML, 4, "jml", AddressingMode::Implied, 4}, // 5C
421  {&CPU::EOR, 4, "eor", AddressingMode::AbsoluteIndexedByX, 3}, // 5D
422  {&CPU::LSR, 7, "lsr", AddressingMode::AbsoluteIndexedByX, 3}, // 5E
423  {&CPU::EOR, 5, "eor", AddressingMode::AbsoluteIndexedByXLong, 4}, // 5F
424  {&CPU::RTS, 6, "rts", AddressingMode::Implied, 1}, // 60
425  {&CPU::ADC, 6, "adc", AddressingMode::DirectPageIndirectIndexedByX, 2}, // 61
426  {&CPU::PER, 6, "per", AddressingMode::Immediate16bits, 3}, // 62
427  {&CPU::ADC, 4, "adc", AddressingMode::StackRelative, 2}, // 63
428  {&CPU::STZ, 3, "stz", AddressingMode::DirectPage, 2}, // 64
429  {&CPU::ADC, 3, "adc", AddressingMode::DirectPage, 2}, // 65
430  {&CPU::ROR, 5, "ror", AddressingMode::DirectPage, 2}, // 66
431  {&CPU::ADC, 6, "adc", AddressingMode::DirectPageIndirectLong, 2}, // 67
432  {&CPU::PLA, 4, "pla", AddressingMode::Implied, 1}, // 68
433  {&CPU::ADC, 2, "adc", AddressingMode::ImmediateForA, 2}, // 69
434  {&CPU::ROR, 2, "ror", AddressingMode::Implied, 1}, // 6A
435  {&CPU::RTL, 6, "rtl", AddressingMode::Implied, 1}, // 6B
436  {&CPU::JMP, 5, "jmp", AddressingMode::AbsoluteIndirect, 3}, // 6C
437  {&CPU::ADC, 4, "adc", AddressingMode::Absolute, 3}, // 6D
438  {&CPU::ROR, 6, "ror", AddressingMode::Absolute, 3}, // 6E
439  {&CPU::ADC, 5, "adc", AddressingMode::AbsoluteLong, 4}, // 6F
440  {&CPU::BVS, 2, "bvs", AddressingMode::Immediate8bits, 2}, // 70
441  {&CPU::ADC, 5, "adc", AddressingMode::DirectPageIndirectIndexedByY, 2}, // 71
442  {&CPU::ADC, 5, "adc", AddressingMode::DirectPageIndirect, 2}, // 72
443  {&CPU::ADC, 7, "adc", AddressingMode::StackRelativeIndirectIndexedByY, 2}, // 73
444  {&CPU::STZ, 4, "stz", AddressingMode::DirectPageIndexedByX, 2}, // 74
445  {&CPU::ADC, 4, "adc", AddressingMode::DirectPageIndexedByX, 2}, // 75
446  {&CPU::ROR, 6, "ror", AddressingMode::DirectPageIndexedByX, 2}, // 76
447  {&CPU::ADC, 6, "adc", AddressingMode::DirectPageIndirectIndexedByY, 2}, // 77
448  {&CPU::SEI, 2, "sei", AddressingMode::Implied, 1}, // 78
449  {&CPU::ADC, 4, "adc", AddressingMode::AbsoluteIndexedByY, 2}, // 79
450  {&CPU::PLY, 4, "ply", AddressingMode::Implied, 1}, // 7A
451  {&CPU::TDC, 2, "tdc", AddressingMode::Implied, 1}, // 7B
452  {&CPU::JMP, 6, "jmp", AddressingMode::AbsoluteIndirectIndexedByX, 3}, // 7C
453  {&CPU::ADC, 4, "adc", AddressingMode::AbsoluteIndexedByX, 3}, // 7D
454  {&CPU::ROR, 7, "ror", AddressingMode::AbsoluteIndexedByX, 3}, // 7E
455  {&CPU::ADC, 5, "adc", AddressingMode::AbsoluteIndexedByXLong, 4}, // 7F
456  {&CPU::BRA, 3, "bra", AddressingMode::Immediate8bits, 2}, // 80
457  {&CPU::STA, 6, "sta", AddressingMode::DirectPageIndexedByX, 2}, // 81
458  {&CPU::BRL, 4, "brl", AddressingMode::Absolute, 3}, // 82
459  {&CPU::STA, 4, "sta", AddressingMode::StackRelative, 2}, // 83
460  {&CPU::STY, 3, "sty", AddressingMode::DirectPage, 2}, // 84
461  {&CPU::STA, 3, "sta", AddressingMode::DirectPage, 2}, // 85
462  {&CPU::STX, 3, "stx", AddressingMode::DirectPage, 2}, // 86
463  {&CPU::STA, 6, "sta", AddressingMode::DirectPageIndirectLong, 2}, // 87
464  {&CPU::DEY, 2, "dey", AddressingMode::Implied, 1}, // 88
465  {&CPU::BIT, 2, "bit", AddressingMode::ImmediateForA, 2}, // 89
466  {&CPU::TXA, 2, "txa", AddressingMode::Implied, 2}, // 8A
467  {&CPU::PHB, 3, "phb", AddressingMode::Implied, 1}, // 8B
468  {&CPU::STY, 4, "sty", AddressingMode::Absolute, 3}, // 8C
469  {&CPU::STA, 4, "sta", AddressingMode::Absolute, 3}, // 8D
470  {&CPU::STX, 4, "stx", AddressingMode::Absolute, 3}, // 8E
471  {&CPU::STA, 5, "sta", AddressingMode::AbsoluteLong, 4}, // 8F
472  {&CPU::BCC, 2, "bcc", AddressingMode::Immediate8bits, 2}, // 90
473  {&CPU::STA, 6, "sta", AddressingMode::DirectPageIndirectIndexedByY, 2}, // 91
474  {&CPU::STA, 5, "sta", AddressingMode::DirectPageIndirect, 2}, // 92
475  {&CPU::STA, 7, "sta", AddressingMode::StackRelativeIndirectIndexedByY, 2}, // 93
476  {&CPU::STY, 4, "sty", AddressingMode::DirectPageIndirectIndexedByX, 2}, // 94
477  {&CPU::STA, 4, "sta", AddressingMode::DirectPageIndexedByX, 2}, // 95
478  {&CPU::STX, 4, "stx", AddressingMode::DirectPageIndexedByY, 2}, // 96
479  {&CPU::STA, 6, "sta", AddressingMode::DirectPageIndirectIndexedByYLong, 2}, // 97
480  {&CPU::TYA, 2, "tya", AddressingMode::Implied, 1}, // 98
481  {&CPU::STA, 5, "sta", AddressingMode::AbsoluteIndexedByY, 3}, // 99
482  {&CPU::TXS, 2, "txs", AddressingMode::Implied, 1}, // 9A
483  {&CPU::TXY, 2, "txy", AddressingMode::Implied, 1}, // 9B
484  {&CPU::STZ, 4, "stz", AddressingMode::Absolute, 3}, // 9C
485  {&CPU::STA, 5, "sta", AddressingMode::AbsoluteIndexedByX, 3}, // 9D
486  {&CPU::STZ, 5, "stz", AddressingMode::AbsoluteIndexedByX, 3}, // 9E
487  {&CPU::STA, 5, "sta", AddressingMode::AbsoluteIndexedByXLong, 4}, // 9F
488  {&CPU::LDY, 2, "ldy", AddressingMode::ImmediateForX, 2}, // A0
489  {&CPU::LDA, 6, "lda", AddressingMode::DirectPageIndirectIndexedByX, 2}, // A1
490  {&CPU::LDX, 2, "ldx", AddressingMode::ImmediateForX, 2}, // A2
491  {&CPU::LDA, 4, "lda", AddressingMode::StackRelative, 2}, // A3
492  {&CPU::LDY, 3, "ldy", AddressingMode::DirectPage, 2}, // A4
493  {&CPU::LDA, 3, "lda", AddressingMode::DirectPage, 2}, // A5
494  {&CPU::LDX, 3, "ldx", AddressingMode::DirectPage, 2}, // A6
495  {&CPU::LDA, 6, "lda", AddressingMode::DirectPageIndirectLong, 2}, // A7
496  {&CPU::TAY, 2, "tay", AddressingMode::Implied, 1}, // A8
497  {&CPU::LDA, 2, "lda", AddressingMode::ImmediateForA, 2}, // A9
498  {&CPU::TAX, 2, "tax", AddressingMode::Implied, 1}, // AA
499  {&CPU::PLB, 4, "plb", AddressingMode::Implied, 1}, // AB
500  {&CPU::LDY, 4, "ldy", AddressingMode::Absolute, 4}, // AC
501  {&CPU::LDA, 4, "lda", AddressingMode::Absolute, 3}, // AD
502  {&CPU::LDX, 4, "ldx", AddressingMode::Absolute, 3}, // AE
503  {&CPU::LDA, 5, "lda", AddressingMode::AbsoluteLong, 4}, // AF
504  {&CPU::BCS, 2, "bcs", AddressingMode::Immediate8bits, 2}, // B0
505  {&CPU::LDA, 5, "lda", AddressingMode::DirectPageIndirectIndexedByY, 2}, // B1
506  {&CPU::LDA, 5, "lda", AddressingMode::DirectPageIndirect, 2}, // B2
507  {&CPU::LDA, 7, "lda", AddressingMode::StackRelativeIndirectIndexedByY, 2}, // B3
508  {&CPU::LDY, 4, "ldy", AddressingMode::DirectPageIndexedByX, 2}, // B4
509  {&CPU::LDA, 4, "lda", AddressingMode::DirectPageIndexedByX, 2}, // B5
510  {&CPU::LDX, 4, "ldx", AddressingMode::DirectPageIndexedByY, 2}, // B6
511  {&CPU::LDA, 6, "lda", AddressingMode::DirectPageIndirectIndexedByYLong, 2}, // B7
512  {&CPU::CLV, 7, "clv", AddressingMode::Implied, 1}, // B8
513  {&CPU::LDA, 4, "lda", AddressingMode::AbsoluteIndexedByY, 3}, // B9
514  {&CPU::TSX, 2, "tsx", AddressingMode::Implied, 1}, // BA
515  {&CPU::TYX, 2, "tyx", AddressingMode::Implied, 1}, // BB
516  {&CPU::LDY, 4, "ldy", AddressingMode::AbsoluteIndexedByX, 3}, // BC
517  {&CPU::LDA, 4, "lda", AddressingMode::AbsoluteIndexedByX, 3}, // BD
518  {&CPU::LDX, 4, "ldx", AddressingMode::AbsoluteIndexedByY, 3}, // BE
519  {&CPU::LDA, 5, "lda", AddressingMode::AbsoluteIndexedByXLong, 4}, // BF
520  {&CPU::CPY, 2, "cpy", AddressingMode::ImmediateForX, 2}, // C0
521  {&CPU::CMP, 6, "cmp", AddressingMode::DirectPageIndirectIndexedByX, 2}, // C1
522  {&CPU::REP, 3, "rep", AddressingMode::Immediate8bits, 2}, // C2
523  {&CPU::CMP, 4, "cmp", AddressingMode::StackRelative, 2}, // C3
524  {&CPU::CPY, 3, "cpy", AddressingMode::DirectPage, 2}, // C4
525  {&CPU::CMP, 3, "cmp", AddressingMode::DirectPage, 2}, // C5
526  {&CPU::DEC, 5, "dec", AddressingMode::DirectPage, 2}, // C6
527  {&CPU::CMP, 6, "cmp", AddressingMode::DirectPageIndirectLong, 2}, // C7
528  {&CPU::INY, 2, "iny", AddressingMode::Implied, 1}, // C8
529  {&CPU::CMP, 2, "cmp", AddressingMode::ImmediateForA, 2}, // C9
530  {&CPU::DEX, 2, "dex", AddressingMode::Implied, 1}, // CA
531  {&CPU::WAI, 3, "wai", AddressingMode::Implied, 1}, // CB
532  {&CPU::CPY, 4, "cpy", AddressingMode::Absolute, 3}, // CC
533  {&CPU::CMP, 4, "cmp", AddressingMode::Absolute, 3}, // CD
534  {&CPU::DEC, 6, "dec", AddressingMode::Absolute, 3}, // CE
535  {&CPU::CMP, 6, "cmp", AddressingMode::AbsoluteLong, 4}, // CF
536  {&CPU::BNE, 2, "bne", AddressingMode::Immediate8bits, 2}, // D0
537  {&CPU::CMP, 5, "cmp", AddressingMode::DirectPageIndirectIndexedByY, 2}, // D1
538  {&CPU::CMP, 5, "cmp", AddressingMode::DirectPageIndirect, 2}, // D2
539  {&CPU::CMP, 7, "cmp", AddressingMode::StackRelativeIndirectIndexedByY, 2}, // D3
540  {&CPU::PEI, 6, "pei", AddressingMode::DirectPage, 2}, // D4
541  {&CPU::CMP, 4, "cmp", AddressingMode::DirectPageIndexedByX, 2}, // D5
542  {&CPU::DEC, 6, "dec", AddressingMode::DirectPageIndexedByX, 2}, // D6
543  {&CPU::CMP, 6, "cmp", AddressingMode::DirectPageIndirectIndexedByYLong, 2}, // D7
544  {&CPU::CLD, 2, "cld", AddressingMode::Implied, 2}, // D8
545  {&CPU::CMP, 4, "cmp", AddressingMode::AbsoluteIndexedByY, 3}, // D9
546  {&CPU::PHX, 3, "phx", AddressingMode::Implied, 1}, // DA
547  {&CPU::STP, 3, "stp", AddressingMode::Implied, 1}, // DB
548  {&CPU::JML, 7, "jml", AddressingMode::AbsoluteIndirectLong, 2}, // DC
549  {&CPU::CMP, 4, "cmp", AddressingMode::AbsoluteIndexedByX, 3}, // DD
550  {&CPU::DEC, 7, "dec", AddressingMode::AbsoluteIndexedByX, 3}, // DE
551  {&CPU::CMP, 5, "cmp", AddressingMode::AbsoluteIndexedByXLong, 4}, // DF
552  {&CPU::CPX, 2, "cpx", AddressingMode::ImmediateForX, 2}, // E0
553  {&CPU::SBC, 6, "sbc", AddressingMode::DirectPageIndirectIndexedByX, 2}, // E1
554  {&CPU::SEP, 3, "sep", AddressingMode::Immediate8bits, 2}, // E2
555  {&CPU::SBC, 4, "sbc", AddressingMode::StackRelative, 2}, // E3
556  {&CPU::CPX, 3, "cpx", AddressingMode::DirectPage, 2}, // E4
557  {&CPU::SBC, 3, "sbc", AddressingMode::DirectPage, 2}, // E5
558  {&CPU::INC, 5, "inc", AddressingMode::DirectPage, 2}, // E6
559  {&CPU::SBC, 6, "sbc", AddressingMode::DirectPageIndirectLong, 2}, // E7
560  {&CPU::INX, 2, "inx", AddressingMode::Implied, 1}, // E8
561  {&CPU::SBC, 2, "sbc", AddressingMode::ImmediateForA, 2}, // E9
562  {&CPU::NOP, 2, "nop", AddressingMode::Implied, 1}, // EA
563  {&CPU::XBA, 3, "xba", AddressingMode::Implied, 1}, // EB
564  {&CPU::CPX, 4, "cpx", AddressingMode::Absolute, 3}, // EC
565  {&CPU::SBC, 4, "sbc", AddressingMode::Absolute, 3}, // ED
566  {&CPU::INC, 6, "inc", AddressingMode::Absolute, 3}, // EE
567  {&CPU::SBC, 5, "sbc", AddressingMode::AbsoluteLong, 4}, // EF
568  {&CPU::BEQ, 2, "beq", AddressingMode::Immediate8bits, 2}, // F0
569  {&CPU::SBC, 5, "sbc", AddressingMode::DirectPageIndirectIndexedByY, 2}, // F1
570  {&CPU::SBC, 5, "sbc", AddressingMode::DirectPageIndirect, 2}, // F2
571  {&CPU::SBC, 7, "sbc", AddressingMode::StackRelativeIndirectIndexedByY, 2}, // F3
572  {&CPU::PEA, 5, "pea", AddressingMode::Immediate16bits, 3}, // F4
573  {&CPU::SBC, 4, "sbc", AddressingMode::DirectPageIndexedByX, 2}, // F5
574  {&CPU::INC, 6, "inc", AddressingMode::DirectPageIndexedByX, 2}, // F6
575  {&CPU::SBC, 6, "sbc", AddressingMode::DirectPageIndirectIndexedByYLong, 2}, // F7
576  {&CPU::SED, 2, "sed", AddressingMode::Implied, 1}, // F8
577  {&CPU::SBC, 4, "sbc", AddressingMode::AbsoluteIndexedByY, 3}, // F9
578  {&CPU::PLX, 4, "plx", AddressingMode::Implied, 1}, // FA
579  {&CPU::XCE, 2, "xce", AddressingMode::Implied, 1}, // FB
580  {&CPU::JSR, 8, "jsr", AddressingMode::AbsoluteIndirectIndexedByX, 3}, // FC
581  {&CPU::SBC, 4, "sbc", AddressingMode::AbsoluteIndexedByX, 3}, // FD
582  {&CPU::INC, 7, "inc", AddressingMode::AbsoluteIndexedByX, 3}, // FE
583  {&CPU::SBC, 5, "sbc", AddressingMode::AbsoluteIndexedByXLong, 4}, // FF
584  };
585 
589  CPU(Memory::IMemoryBus &bus, Cartridge::Header &cartridgeHeader);
591  CPU(const CPU &) = default;
593  CPU &operator=(const CPU &) = delete;
595  ~CPU() override = default;
596 
600  unsigned update(unsigned maxCycle);
601 
604  unsigned executeInstruction();
605 
609  unsigned runDMA(unsigned maxCycles);
610 
615  uint8_t read(uint24_t addr) override;
620  void write(uint24_t addr, uint8_t data) override;
621 
624  [[nodiscard]] std::string getValueName(uint24_t addr) const override;
625 
628  [[nodiscard]] uint24_t getSize() const override;
629 
631  [[nodiscard]] std::string getName() const override;
632 
634  [[nodiscard]] Component getComponent() const override;
635 
638  int RESB();
639 
641  Callback<> onReset;
642 
644  bool IsNMIRequested = false;
646  bool IsIRQRequested = false;
648  bool IsAbortRequested = false;
649 
651  bool isDisabled = false;
652 
653 #ifdef DEBUGGER_ENABLED
654  friend Debugger::CPU::CPUDebug;
655  friend Debugger::RegisterViewer;
656 #endif
657  };
658 }
ComSquare::CPU::CPU::PHB
int PHB(uint24_t, AddressingMode)
Push the data bank register to the stack.
Definition: InternalInstruction.cpp:92
ComSquare::Debugger::RegisterViewer
Definition: RegisterViewer.hpp:49
ComSquare::CPU::CPU::TXA
int TXA(uint24_t, AddressingMode)
Transfer X to A.
Definition: TransferRegisters.cpp:97
ComSquare::CPU::CPU::PLD
int PLD(uint24_t, AddressingMode)
Pull the direct page register to the stack.
Definition: InternalInstruction.cpp:148
MemoryBus.hpp
Ints.hpp
ComSquare::CPU::CPU::_hasIndexCrossedPageBoundary
bool _hasIndexCrossedPageBoundary
True if an addressing mode with an iterator (x, y) has crossed the page. (Used because crossing the p...
Definition: CPU.hpp:50
ComSquare::CPU::CPU::INX
int INX(uint24_t, AddressingMode)
Increment the X register.
Definition: MathematicalOperations.cpp:189
ComSquare::CPU::CPU::TCS
int TCS(uint24_t, AddressingMode)
Transfer 16 bit A to SP.
Definition: TransferRegisters.cpp:61
ComSquare::CPU::CPU::CPY
int CPY(uint24_t valueAddr, AddressingMode)
Compare the Y register with the memory.
Definition: MathematicalOperations.cpp:235
ComSquare::CPU::CPU::PHA
int PHA(uint24_t, AddressingMode)
Push the accumulator to the stack.
Definition: InternalInstruction.cpp:83
ComSquare::CPU::CPU::_getStackRelativeIndirectIndexedYAddr
uint24_t _getStackRelativeIndirectIndexedYAddr()
The <8-bit exp> is added to S and combined with DBR to form the base address. Y is added to the base ...
Definition: AddressingModes.cpp:188
ComSquare::CPU::CPU::_getDirectIndirectIndexedYLongAddr
uint24_t _getDirectIndirectIndexedYLongAddr()
This mode is like the previous addressing mode, but the difference is that rather than pulling 2 byte...
Definition: AddressingModes.cpp:75
ComSquare::CPU::CPU::SEC
int SEC(uint24_t, AddressingMode)
Set the carry Flag.
Definition: InternalInstruction.cpp:9
ComSquare::Component
Component
Definition: Components.hpp:9
ComSquare::CPU::Registers::pc
uint16_t pc
Definition: Registers.hpp:49
ComSquare::CPU::Implied
@ Implied
Definition: Instruction.hpp:16
ComSquare::CPU::CPU::DEY
int DEY(uint24_t, AddressingMode)
Decrement the Y register.
Definition: MathematicalOperations.cpp:139
DMA.hpp
ComSquare::CPU::CPU::setBus
void setBus(Memory::IMemoryBus &bus)
Set the memory bus used by this CPU.
Definition: CPU.cpp:21
ComSquare::CPU::CPU
The main CPU.
Definition: CPU.hpp:26
ComSquare::CPU::CPU::TYA
int TYA(uint24_t, AddressingMode)
Transfer Y to A.
Definition: TransferRegisters.cpp:113
ComSquare::CPU::CPU::getName
std::string getName() const override
Get the name of this accessor (used for debug purpose)
Definition: CPU.cpp:355
ComSquare::CPU::CPU::_getImmediateAddr8Bits
uint24_t _getImmediateAddr8Bits()
Immediate address mode is specified with a value in 8 bits. (This functions returns the 24bit space a...
Definition: AddressingModes.cpp:10
ComSquare::Memory::IMemoryBus::read
virtual uint8_t read(uint24_t addr)=0
Read data at a global address. This form allow read to be silenced.
ComSquare::CPU::CPU::_isStopped
bool _isStopped
If the processor is stopped (using an STP instruction), the clock is stopped and no instruction will ...
Definition: CPU.hpp:37
ComSquare::CPU::CPU::BVS
int BVS(uint24_t valueAddr, AddressingMode)
Branch if Overflow Set.
Definition: InternalInstruction.cpp:290
ComSquare::CPU::CPU::_getDirectIndirectAddr
uint24_t _getDirectIndirectAddr()
2 bytes are pulled from the direct page address to form the 16-bit address. It is combined with DBR t...
Definition: AddressingModes.cpp:165
Callback.hpp
ComSquare::CPU::CPU::MVN
int MVN(uint24_t, AddressingMode)
Block Move Next. This instruction is special: it takes parameter in the registers.
Definition: TransferRegisters.cpp:155
ComSquare::CPU::CPU::RTI
int RTI(uint24_t, AddressingMode)
Return from Interrupt - Used to return from a interrupt handler.
Definition: Interrupts.cpp:62
ComSquare::CPU::CPU::BMI
int BMI(uint24_t valueAddr, AddressingMode)
Branch if minus.
Definition: InternalInstruction.cpp:254
ComSquare::CPU::CPU::_getDirectIndirectIndexedXAddr
uint24_t _getDirectIndirectIndexedXAddr()
The direct page address is calculated and added with x. 2 bytes from the dp address combined with DBR...
Definition: AddressingModes.cpp:84
ComSquare::CPU::CPU::instructions
const Instruction instructions[0x100]
All the instructions of the CPU. @info Instructions are indexed by their opcode.
Definition: CPU.hpp:327
ComSquare::CPU::CPU::BVC
int BVC(uint24_t valueAddr, AddressingMode)
Branch if Overflow Clear.
Definition: InternalInstruction.cpp:283
ComSquare::CPU::CPU::CPU
CPU(Memory::IMemoryBus &bus, Cartridge::Header &cartridgeHeader)
Construct a new generic CPU.
Definition: CPU.cpp:13
ComSquare::CPU::CPU::ROL
int ROL(uint24_t, AddressingMode)
Definition: BitsInstructions.cpp:158
ComSquare::CPU::AbsoluteIndirectIndexedByX
@ AbsoluteIndirectIndexedByX
Definition: Instruction.hpp:45
ComSquare::CPU::DirectPageIndirectIndexedByX
@ DirectPageIndirectIndexedByX
Definition: Instruction.hpp:36
ComSquare::CPU::CPU::PEI
int PEI(uint24_t, AddressingMode)
Push Effective Indirect Address.
Definition: InternalInstruction.cpp:205
ComSquare::CPU::CPU::RTL
int RTL(uint24_t, AddressingMode)
Return from subroutine long.
Definition: InternalInstruction.cpp:320
AMemory.hpp
ComSquare::CPU::AbsoluteLong
@ AbsoluteLong
Definition: Instruction.hpp:24
ComSquare::CPU::StackRelativeIndirectIndexedByY
@ StackRelativeIndirectIndexedByY
Definition: Instruction.hpp:41
ComSquare::CPU::CPU::CLV
int CLV(uint24_t, AddressingMode)
Clear the overflow flag.
Definition: InternalInstruction.cpp:45
ComSquare::CPU::CPU::MVP
int MVP(uint24_t, AddressingMode)
Block Move Previous. This instruction is special: it takes parameter in the registers.
Definition: TransferRegisters.cpp:172
ComSquare::CPU::DirectPageIndirect
@ DirectPageIndirect
Definition: Instruction.hpp:27
ComSquare::CPU::CPU::_isEmulationMode
bool _isEmulationMode
Is the CPU running in emulation mode (in 8bits)
Definition: CPU.hpp:35
ComSquare::CPU::AbsoluteIndexedByX
@ AbsoluteIndexedByX
Definition: Instruction.hpp:30
ComSquare::CPU::CPU::_getImmediateAddr16Bits
uint24_t _getImmediateAddr16Bits()
Immediate address mode is specified with a value in 16 bits. (This functions returns the 24bit space ...
Definition: AddressingModes.cpp:17
ComSquare::CPU::CPU::TSC
int TSC(uint24_t, AddressingMode)
Transfer DP to 16 bit A.
Definition: TransferRegisters.cpp:77
ComSquare::CPU::CPU::write
void write(uint24_t addr, uint8_t data) override
Write data to the internal CPU register.
Definition: CPU.cpp:103
ComSquare::CPU::CPU::STX
int STX(uint24_t addr, AddressingMode)
Store the index register X to memory.
Definition: MemoryInstructions.cpp:34
Cartridge.hpp
ComSquare::CPU::CPU::JML
int JML(uint24_t valueAddr, AddressingMode)
Long jump.
Definition: InternalInstruction.cpp:303
ComSquare::CPU::CPU::NOP
int NOP(uint24_t, AddressingMode)
No OP.
Definition: InternalInstruction.cpp:309
ComSquare::CPU::CPU::ROR
int ROR(uint24_t, AddressingMode)
Definition: BitsInstructions.cpp:201
ComSquare::CPU::CPU::PHD
int PHD(uint24_t, AddressingMode)
Push the direct page register to the stack.
Definition: InternalInstruction.cpp:98
ComSquare::CPU::CPU::ASL
int ASL(uint24_t, AddressingMode)
Arithmetic Shift Left.
Definition: BitsInstructions.cpp:80
ComSquare::CPU::CPU::_getImmediateAddrForX
uint24_t _getImmediateAddrForX()
Immediate address mode is specified with a value in 8 or 16 bits. The value is 16 bits if the x flag ...
Definition: AddressingModes.cpp:33
ComSquare::CPU
Definition: AddressingModes.cpp:8
ComSquare::CPU::CPU::_cartridgeHeader
Cartridge::Header & _cartridgeHeader
The cartridge header (stored for interrupt vectors..)
Definition: CPU.hpp:44
ComSquare::CPU::CPU::WDM
int WDM(uint24_t, AddressingMode)
WDM Reserved for Future Expansion (used as a code breakpoint)
Definition: InternalInstruction.cpp:333
ComSquare::CPU::CPU::EOR
int EOR(uint24_t, AddressingMode)
XOR, Exclusive OR accumulator with memory.
Definition: MathematicalOperations.cpp:369
ComSquare::CPU::Instruction
Struct containing basic information about instructions.
Definition: Instruction.hpp:51
ComSquare::CPU::CPU::_getAbsoluteIndirectAddr
uint24_t _getAbsoluteIndirectAddr()
2 bytes are pulled from the <abs exp> to form the effective address.
Definition: AddressingModes.cpp:136
ComSquare::CPU::CPU::TAY
int TAY(uint24_t, AddressingMode)
Transfer A to Y.
Definition: TransferRegisters.cpp:24
ComSquare::CPU::CPU::INC
int INC(uint24_t, AddressingMode)
Increment.
Definition: MathematicalOperations.cpp:289
ComSquare::CPU::CPU::STA
int STA(uint24_t addr, AddressingMode)
Store the accumulator to memory.
Definition: MemoryInstructions.cpp:9
ComSquare::CPU::CPU::_pop
uint8_t _pop()
Pop 8 bits of data from the stack.
Definition: CPU.cpp:343
uint24_t
unsigned uint24_t
Definition: Ints.hpp:10
ComSquare::CPU::AbsoluteIndexedByY
@ AbsoluteIndexedByY
Definition: Instruction.hpp:32
ComSquare::CPU::CPU::PHK
int PHK(uint24_t, AddressingMode)
Push the program bank register to the stack.
Definition: InternalInstruction.cpp:104
ComSquare::CPU::CPU::SBC
int SBC(uint24_t valueAddr, AddressingMode)
Subtract with Borrow from Accumulator.
Definition: MathematicalOperations.cpp:52
ComSquare::CPU::CPU::DEC
int DEC(uint24_t, AddressingMode)
Decrement.
Definition: MathematicalOperations.cpp:329
ComSquare::CPU::CPU::PLA
int PLA(uint24_t, AddressingMode)
Pull the accumulator to the stack.
Definition: InternalInstruction.cpp:128
ComSquare::CPU::CPU::PLB
int PLB(uint24_t, AddressingMode)
Pull the data bank register to the stack.
Definition: InternalInstruction.cpp:140
ComSquare::CPU::ImmediateForX
@ ImmediateForX
Definition: Instruction.hpp:21
ComSquare::CPU::CPU::update
unsigned update(unsigned maxCycle)
This function continue to execute the Cartridge code.
Definition: CPU.cpp:210
ComSquare::CPU::CPU::_getAbsoluteLongAddr
uint24_t _getAbsoluteLongAddr()
The effective address is the expression. (This functions returns the 24bit space address of the value...
Definition: AddressingModes.cpp:56
ComSquare::CPU::CPU::_getAbsoluteIndexedByXAddr
uint24_t _getAbsoluteIndexedByXAddr()
The absolute expression is added with X and combined with DBR to form the effective address.
Definition: AddressingModes.cpp:108
ComSquare::CPU::CPU::ADC
int ADC(uint24_t valueAddr, AddressingMode)
Add with carry - Adds operand to the Accumulator; adds an additional 1 if carry is set.
Definition: MathematicalOperations.cpp:10
ComSquare::CPU::CPU::PHP
int PHP(uint24_t, AddressingMode)
Push the processor status register to the stack.
Definition: InternalInstruction.cpp:110
ComSquare::CPU::CPU::STZ
int STZ(uint24_t addr, AddressingMode)
Store zero to the memory.
Definition: MemoryInstructions.cpp:56
ComSquare::CPU::CPU::_dmaChannels
std::array< DMA, 8 > _dmaChannels
DMA channels witch are mapped to the bus.
Definition: CPU.hpp:47
ComSquare::CPU::CPU::_readPC
uint8_t _readPC()
Return the data at the program bank concatenated with the program counter. It also increment the prog...
Definition: CPU.hpp:107
ComSquare::CPU::CPU::_getAbsoluteAddr
uint24_t _getAbsoluteAddr()
The effective address is formed by DBR:<16-bit exp>. (This functions returns the 24bit space address ...
Definition: AddressingModes.cpp:48
ComSquare::CPU::CPU::TSX
int TSX(uint24_t, AddressingMode)
Transfer SP to X.
Definition: TransferRegisters.cpp:85
ComSquare::CPU::CPU::TAX
int TAX(uint24_t, AddressingMode)
Transfer A to X.
Definition: TransferRegisters.cpp:10
ComSquare::CPU::CPU::CLC
int CLC(uint24_t, AddressingMode)
Clear the carry flag.
Definition: InternalInstruction.cpp:27
ComSquare::CPU::CPU::LDY
int LDY(uint24_t addr, AddressingMode)
Load the Y index register from memory.
Definition: MemoryInstructions.cpp:128
ComSquare::CPU::ImmediateForA
@ ImmediateForA
Definition: Instruction.hpp:20
ComSquare::CPU::CPU::BPL
int BPL(uint24_t valueAddr, AddressingMode)
Branch if plus.
Definition: InternalInstruction.cpp:261
ComSquare::CPU::CPU::JSL
int JSL(uint24_t addr, AddressingMode)
Jump to subroutine (long)
Definition: InternalInstruction.cpp:74
ComSquare::CPU::CPU::getComponent
Component getComponent() const override
Get the component of this accessor (used for debug purpose)
Definition: CPU.cpp:360
ComSquare::CPU::CPU::BIT
int BIT(uint24_t, AddressingMode)
Test Memory Bits against Accumulator.
Definition: BitsInstructions.cpp:52
ComSquare::CPU::CPU::_getDirectIndirectIndexedYAddr
uint24_t _getDirectIndirectIndexedYAddr()
The address is DBR:$(read($($Value + D)) + Y). (This functions returns the 24bit space address of the...
Definition: AddressingModes.cpp:64
ComSquare::CPU::CPU::STP
int STP(uint24_t, AddressingMode)
Stop the processor.
Definition: InternalInstruction.cpp:327
ComSquare::CPU::DirectPage
@ DirectPage
Definition: Instruction.hpp:26
ComSquare::CPU::CPU::_isWaitingForInterrupt
bool _isWaitingForInterrupt
Is the processor waiting for an interrupt (if true, instructions are not run until an interrupt is re...
Definition: CPU.hpp:39
ComSquare::CPU::CPU::SED
int SED(uint24_t, AddressingMode)
Set the decimal flag.
Definition: InternalInstruction.cpp:15
ComSquare::Memory::IMemoryBus
The memory bus is the component responsible of mapping addresses to components address and transmitti...
Definition: IMemoryBus.hpp:19
ComSquare::CPU::DirectPageIndirectIndexedByYLong
@ DirectPageIndirectIndexedByYLong
Definition: Instruction.hpp:38
ComSquare::CPU::CPU::TDC
int TDC(uint24_t, AddressingMode)
Transfer DP to 16 bit A.
Definition: TransferRegisters.cpp:69
ComSquare::CPU::StackRelative
@ StackRelative
Definition: Instruction.hpp:40
ComSquare::CPU::DirectPageIndirectIndexedByY
@ DirectPageIndirectIndexedByY
Definition: Instruction.hpp:37
ComSquare::CPU::CPU::LSR
int LSR(uint24_t, AddressingMode)
Definition: BitsInstructions.cpp:120
ComSquare::CPU::CPU::TXY
int TXY(uint24_t, AddressingMode)
Transfer X to Y.
Definition: TransferRegisters.cpp:129
ComSquare::CPU::CPU::read
uint8_t read(uint24_t addr) override
Read from the internal CPU register.
Definition: CPU.cpp:29
ComSquare::CPU::CPU::getValueName
std::string getValueName(uint24_t addr) const override
Get the name of the data at the address.
Definition: TransferRegisters.cpp:189
ComSquare::CPU::DirectPageIndirectLong
@ DirectPageIndirectLong
Definition: Instruction.hpp:28
ComSquare::CPU::CPU::LDX
int LDX(uint24_t addr, AddressingMode)
Load the X index register from memory.
Definition: MemoryInstructions.cpp:101
ComSquare::CPU::CPU::_runInterrupt
void _runInterrupt(uint24_t nativeHandler, uint24_t emulationHandler)
Run an interrupt (save state of the processor and jump to the interrupt handler)
Definition: Interrupts.cpp:26
ComSquare::CPU::Immediate16bits
@ Immediate16bits
Definition: Instruction.hpp:19
ComSquare::CPU::DirectPageIndexedByX
@ DirectPageIndexedByX
Definition: Instruction.hpp:34
ComSquare::CPU::InternalRegisters
Struct containing internal registers of the CPU.
Definition: Registers.hpp:115
Registers.hpp
ComSquare::CPU::CPU::BRK
int BRK(uint24_t, AddressingMode)
Break instruction - Causes a software break. The PC is loaded from a vector table.
Definition: Interrupts.cpp:46
ComSquare::CPU::CPU::IsIRQRequested
bool IsIRQRequested
Is an interrupt (maskable) requested.
Definition: CPU.hpp:646
ComSquare::CPU::CPU::_getAbsoluteIndirectLongAddr
uint24_t _getAbsoluteIndirectLongAddr()
3 bytes are pulled from the <abs exp> to form the effective address.
Definition: AddressingModes.cpp:145
ComSquare::CPU::CPU::BRA
int BRA(uint24_t valueAddr, AddressingMode)
Branch always.
Definition: InternalInstruction.cpp:268
ComSquare::Debugger::CPU::CPUDebug
A window that show registers and the disassembly of a CPU.
Definition: CPUDebug.hpp:201
ComSquare::CPU::CPU::PLX
int PLX(uint24_t, AddressingMode)
Pull the x index register to the stack.
Definition: InternalInstruction.cpp:166
ComSquare::CPU::CPU::_getDirectIndexedByXAddr
uint24_t _getDirectIndexedByXAddr()
The DP address is added to X to form the effective address. The effective address is always in bank 0...
Definition: AddressingModes.cpp:94
ComSquare::CPU::CPU::_internalRegisters
InternalRegisters _internalRegisters
Internal registers of the CPU (accessible from the bus via addr $4200 to $421F).
Definition: CPU.hpp:32
ComSquare::CPU::AbsoluteIndexedByXLong
@ AbsoluteIndexedByXLong
Definition: Instruction.hpp:31
ComSquare::CPU::CPU::INY
int INY(uint24_t, AddressingMode)
Increment the Y register.
Definition: MathematicalOperations.cpp:202
ComSquare::CPU::CPU::CLD
int CLD(uint24_t, AddressingMode)
Clear the decimal flag.
Definition: InternalInstruction.cpp:39
ComSquare::CPU::CPU::PLY
int PLY(uint24_t, AddressingMode)
Pull the y index register to the stack.
Definition: InternalInstruction.cpp:178
ComSquare::CPU::CPU::RESB
int RESB()
Reset interrupt - Called on boot and when the reset button is pressed.
Definition: Interrupts.cpp:9
ComSquare::CPU::CPU::_getDirectIndexedByYAddr
uint24_t _getDirectIndexedByYAddr()
The DP address is added to Y to form the effective address. The effective address is always in bank 0...
Definition: AddressingModes.cpp:101
ComSquare::CPU::CPU::TYX
int TYX(uint24_t, AddressingMode)
Transfer Y to X.
Definition: TransferRegisters.cpp:142
ComSquare::CPU::CPU::_pop16
uint16_t _pop16()
Pop 16 bits of data from the stack.
Definition: CPU.cpp:348
ComSquare::CPU::CPU::_checkInterrupts
void _checkInterrupts()
Check if an interrupt is requested and handle it.
Definition: CPU.cpp:232
ComSquare::Memory::AMemory
Abstract class representing a continuous block of memory.
Definition: AMemory.hpp:18
ComSquare::CPU::CPU::executeInstruction
unsigned executeInstruction()
Execute a single instruction.
Definition: CPU.cpp:323
ComSquare::CPU::CPU::BNE
int BNE(uint24_t valueAddr, AddressingMode)
Branch if not equal.
Definition: InternalInstruction.cpp:247
ComSquare::CPU::Absolute
@ Absolute
Definition: Instruction.hpp:23
RegisterViewer.hpp
ComSquare::CPU::CPU::RTS
int RTS(uint24_t, AddressingMode)
Return from subroutine.
Definition: InternalInstruction.cpp:314
ComSquare::CPU::CPU::TRB
int TRB(uint24_t, AddressingMode)
Test and Reset Memory Bits Against Accumulator.
Definition: BitsInstructions.cpp:31
ComSquare::CPU::CPU::TSB
int TSB(uint24_t, AddressingMode)
Test and Set Memory Bits Against Accumulator.
Definition: BitsInstructions.cpp:11
ComSquare::CPU::CPU::JSR
int JSR(uint24_t addr, AddressingMode)
Jump to subroutine.
Definition: InternalInstruction.cpp:67
ComSquare::CPU::CPU::PER
int PER(uint24_t, AddressingMode)
Push Effective PC Relative Indirect Address.
Definition: InternalInstruction.cpp:190
ComSquare::CPU::AbsoluteIndirectLong
@ AbsoluteIndirectLong
Definition: Instruction.hpp:47
ComSquare::CPU::CPU::XCE
int XCE(uint24_t, AddressingMode)
Exchange Carry and Emulation Flags.
Definition: InternalInstruction.cpp:211
ComSquare::CPU::CPU::_getImmediateAddrForA
uint24_t _getImmediateAddrForA()
Immediate address mode is specified with a value in 8 or 16 bits. The value is 16 bits if the m flag ...
Definition: AddressingModes.cpp:24
ComSquare::Cartridge::Header
Definition: Cartridge.hpp:34
ComSquare::CPU::CPU::XBA
int XBA(uint24_t, AddressingMode)
Exchange the B and A Accumulators.
Definition: MathematicalOperations.cpp:402
ComSquare::CPU::CPU::_getDirectAddr
uint24_t _getDirectAddr()
The destination is formed by adding the direct page register with the 8-bit address to form an effect...
Definition: AddressingModes.cpp:42
ComSquare::CPU::Registers::pac
uint24_t pac
The current Program Address Counter (does not exist in a snes but is useful here).
Definition: Registers.hpp:55
ComSquare::CPU::CPU::AND
int AND(uint24_t valueAddr, AddressingMode)
And accumulator with memory.
Definition: MathematicalOperations.cpp:255
ComSquare::Callback
A callback where you can subscribe to and emit it.
Definition: Callback.hpp:16
ComSquare::CPU::CPU::BCS
int BCS(uint24_t valueAddr, AddressingMode)
Branch if carry set.
Definition: InternalInstruction.cpp:233
ComSquare::CPU::CPU::IsNMIRequested
bool IsNMIRequested
Is an NMI (non-maskable interrupt) requested.
Definition: CPU.hpp:644
ComSquare::CPU::AddressingMode
AddressingMode
Different addressing modes that instructions can use for the main CPU.
Definition: Instruction.hpp:15
ComSquare::CPU::CPU::BEQ
int BEQ(uint24_t valueAddr, AddressingMode)
Branch if equal.
Definition: InternalInstruction.cpp:240
ComSquare::CPU::CPU::getSize
uint24_t getSize() const override
Get the size of the data. This size can be lower than the mapped data.
Definition: CPU.cpp:205
ComSquare::CPU::CPU::REP
int REP(uint24_t valueAddr, AddressingMode)
Reset status bits.
Definition: InternalInstruction.cpp:57
ComSquare::CPU::CPU::IsAbortRequested
bool IsAbortRequested
Is an abort requested.
Definition: CPU.hpp:648
ComSquare::CPU::CPU::WAI
int WAI(uint24_t, AddressingMode)
Wait for Interrupt.
Definition: Interrupts.cpp:72
CPUDebug.hpp
ComSquare::CPU::CPU::CMP
int CMP(uint24_t, AddressingMode)
Compare Accumulator with Memory.
Definition: MathematicalOperations.cpp:151
ComSquare::CPU::CPU::BRL
int BRL(uint24_t valueAddr, AddressingMode)
Branch always long.
Definition: InternalInstruction.cpp:274
ComSquare::CPU::CPU::_getAbsoluteIndexedByXLongAddr
uint24_t _getAbsoluteIndexedByXLongAddr()
The effective address is formed by adding the <long exp> with X.
Definition: AddressingModes.cpp:128
ComSquare::CPU::CPU::_registers
Registers _registers
All the registers of the CPU.
Definition: CPU.hpp:30
ComSquare::CPU::Registers
Struct containing registers for the main CPU.
Definition: Registers.hpp:13
ComSquare::CPU::CPU::_bus
std::reference_wrapper< Memory::IMemoryBus > _bus
The memory bus to use for read/write.
Definition: CPU.hpp:42
ComSquare::CPU::CPU::_getDirectIndirectLongAddr
uint24_t _getDirectIndirectLongAddr()
3 bytes are pulled from the direct page address to form an effective address.
Definition: AddressingModes.cpp:174
ComSquare::CPU::CPU::DEX
int DEX(uint24_t, AddressingMode)
Decrement the X register.
Definition: MathematicalOperations.cpp:127
ComSquare::CPU::CPU::PLP
int PLP(uint24_t, AddressingMode)
Pull the processor status register to the stack.
Definition: InternalInstruction.cpp:156
ComSquare::CPU::CPU::JMP
int JMP(uint24_t valueAddr, AddressingMode)
Jump.
Definition: InternalInstruction.cpp:297
ComSquare::CPU::CPU::_push
void _push(uint8_t data)
Push 8 bits of data to the stack.
Definition: CPU.cpp:332
ComSquare::CPU::CPU::operator=
CPU & operator=(const CPU &)=delete
A CPU is not assignable.
ComSquare::CPU::CPU::TXS
int TXS(uint24_t, AddressingMode)
Transfer X to SP.
Definition: TransferRegisters.cpp:38
ComSquare::CPU::CPU::ORA
int ORA(uint24_t valueAddr, AddressingMode mode)
Or accumulator with memory.
Definition: MathematicalOperations.cpp:94
ComSquare::CPU::CPU::PHX
int PHX(uint24_t, AddressingMode)
Push the x index register to the stack.
Definition: InternalInstruction.cpp:116
ComSquare::CPU::CPU::LDA
int LDA(uint24_t addr, AddressingMode)
Load the accumulator from memory.
Definition: MemoryInstructions.cpp:66
ComSquare::CPU::CPU::BCC
int BCC(uint24_t valueAddr, AddressingMode)
Branch if carry clear.
Definition: InternalInstruction.cpp:226
ComSquare::CPU::CPU::_getAbsoluteIndirectIndexedByXAddr
uint24_t _getAbsoluteIndirectIndexedByXAddr()
The <abs exp> is added with X, then 2 bytes are pulled from that address to form the new location.
Definition: AddressingModes.cpp:155
ComSquare::CPU::CPU::_getAbsoluteIndexedByYAddr
uint24_t _getAbsoluteIndexedByYAddr()
The absolute expression is added with Y and combined with DBR to form the effective address.
Definition: AddressingModes.cpp:118
ComSquare::CPU::CPU::SEP
int SEP(uint24_t valueAddr, AddressingMode)
Set status bits.
Definition: InternalInstruction.cpp:51
ComSquare::CPU::CPU::getBus
Memory::IMemoryBus & getBus()
Get the memory bus used by this CPU.
Definition: CPU.hpp:317
ComSquare::CPU::CPU::SEI
int SEI(uint24_t, AddressingMode)
Set the Interrupt Disable flag.
Definition: InternalInstruction.cpp:21
ComSquare::CPU::DirectPageIndexedByY
@ DirectPageIndexedByY
Definition: Instruction.hpp:35
ComSquare::CPU::CPU::PEA
int PEA(uint24_t, AddressingMode)
Push Effective Absolute Address.
Definition: InternalInstruction.cpp:199
ComSquare::CPU::CPU::PHY
int PHY(uint24_t, AddressingMode)
Push the y index register to the stack.
Definition: InternalInstruction.cpp:122
ComSquare::CPU::CPU::_getStackRelativeAddr
uint24_t _getStackRelativeAddr()
The stack register is added to the <8-bit exp> to form the effective address.
Definition: AddressingModes.cpp:183
ComSquare::CPU::CPU::isDisabled
bool isDisabled
True if you want to disable updates of this CPU.
Definition: CPU.hpp:651
ComSquare::CPU::AbsoluteIndirect
@ AbsoluteIndirect
Definition: Instruction.hpp:44
ComSquare::CPU::CPU::~CPU
~CPU() override=default
A default destructor.
ComSquare::CPU::CPU::CLI
int CLI(uint24_t, AddressingMode)
Clear the Interrupt Disable flag.
Definition: InternalInstruction.cpp:33
Instruction.hpp
ComSquare::CPU::Immediate8bits
@ Immediate8bits
Definition: Instruction.hpp:18
ComSquare::CPU::CPU::COP
int COP(uint24_t, AddressingMode)
Co-Processor Enable instruction - Causes a software break. The PC is loaded from a vector table.
Definition: Interrupts.cpp:54
ComSquare::CPU::CPU::onReset
Callback onReset
The callback triggered on reset.
Definition: CPU.hpp:641
ComSquare::CPU::CPU::runDMA
unsigned runDMA(unsigned maxCycles)
Run DMA's pending transfers.
Definition: CPU.cpp:252
ComSquare::CPU::CPU::CPX
int CPX(uint24_t valueAddr, AddressingMode)
Compare the X register with the memory.
Definition: MathematicalOperations.cpp:215
ComSquare::CPU::CPU::_getValueAddr
uint24_t _getValueAddr(const Instruction &instruction)
Get the parameter address of an instruction from it's addressing mode. @info The current program coun...
Definition: CPU.cpp:264
ComSquare::CPU::CPU::STY
int STY(uint24_t addr, AddressingMode)
Store the index register Y to memory.
Definition: MemoryInstructions.cpp:45
ComSquare::CPU::CPU::TCD
int TCD(uint24_t, AddressingMode)
Transfer 16 bit A to DP.
Definition: TransferRegisters.cpp:53
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