ComSquare
DMA.hpp
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1 //
2 // Created by anonymus-raccoon on 5/26/20.
3 //
4 
5 #pragma once
6 
7 #include "Memory/MemoryBus.hpp"
8 #include "Models/Ints.hpp"
9 #include <cstdint>
10 #include <memory>
11 
12 #ifdef DEBUGGER_ENABLED
14 #endif
15 
16 namespace ComSquare::CPU
17 {
19  class DMA
20  {
21  public:
23  enum DMAMode
24  {
26  OneToOne = 0b000,
28  TwoToTwo = 0b001,
30  TwoToOne = 0b010,
32  FourToTwo = 0b011,
34  FourToFour = 0b100,
36  TwoToTwoBis = 0b101,
38  TwoToOneBis = 0b110,
40  FourToTwoBis = 0b111
41  };
42 
43  enum Direction
44  {
47  };
48 
49  private:
52  unsigned _writeOneByte(uint24_t aAddress, uint24_t bAddress);
54  [[nodiscard]] int _getModeOffset(int index) const;
55 
57  union
58  {
59  struct {
63  bool fixed : 1;
65  bool increment : 1;
67  bool _ : 2;
70  };
71  uint8_t raw;
72  } _controlRegister {};
73 
75  uint8_t _port {};
76 
78  union
79  {
80  uint8_t bytes[3];
81  struct {
82  uint16_t page;
83  uint8_t bank;
84  };
85  uint24_t raw : 24;
86  } _aAddress {};
87 
89  union
90  {
91  uint8_t bytes[2];
92  uint16_t raw;
93  } _count {};
94 
97 
98  public:
100  [[nodiscard]] inline Memory::IMemoryBus &getBus()
101  {
102  return this->_bus;
103  }
106  void setBus(Memory::IMemoryBus &bus);
107 
109  bool enabled;
110 
114  [[nodiscard]] uint8_t read(uint8_t addr) const;
115 
119  void write(uint8_t addr, uint8_t data);
120 
124  unsigned run(unsigned cycles);
125 
128  explicit DMA(Memory::IMemoryBus &bus);
130  DMA(const DMA &) = default;
132  DMA &operator=(const DMA &) = delete;
134  ~DMA() = default;
135 
136 #ifdef DEBUGGER_ENABLED
138 #endif
139  };
140 }// namespace ComSquare::CPU
ComSquare::CPU::DMA::~DMA
~DMA()=default
A default destructor.
ComSquare::Debugger::RegisterViewer
Definition: RegisterViewer.hpp:49
ComSquare::CPU::DMA::fixed
bool fixed
If this flag is set, no increment/decrement will be done.
Definition: DMA.hpp:63
MemoryBus.hpp
Ints.hpp
ComSquare::CPU::DMA::_
bool _
Two unused bites.
Definition: DMA.hpp:67
ComSquare::CPU::DMA::raw
uint16_t raw
Definition: DMA.hpp:92
ComSquare::CPU::DMA::page
uint16_t page
Definition: DMA.hpp:82
ComSquare::CPU::DMA::FourToFour
@ FourToFour
4 byte is transferred to 4 register (write once)
Definition: DMA.hpp:34
ComSquare::CPU::DMA::direction
Direction direction
The direction of the transfer.
Definition: DMA.hpp:69
ComSquare::CPU::DMA::BtoA
@ BtoA
Definition: DMA.hpp:46
ComSquare::CPU::DMA::TwoToOne
@ TwoToOne
2 byte is transferred to 1 register (write twice)
Definition: DMA.hpp:30
ComSquare::CPU::DMA::DMAMode
DMAMode
The first three bytes of the DMA's control register. Used to tell how many bytes/registers there is.
Definition: DMA.hpp:23
ComSquare::CPU::DMA::enabled
bool enabled
Is this channel set to run?
Definition: DMA.hpp:109
ComSquare::CPU::DMA::increment
bool increment
if this flag is 0: increment. Else: decrement. (The A address)
Definition: DMA.hpp:65
ComSquare::CPU
Definition: AddressingModes.cpp:8
ComSquare::CPU::DMA::mode
DMAMode mode
DMA's mode: how many bytes/registers there is, how many writes...
Definition: DMA.hpp:61
uint24_t
unsigned uint24_t
Definition: Ints.hpp:10
ComSquare::CPU::DMA::Direction
Direction
Definition: DMA.hpp:43
ComSquare::CPU::DMA::operator=
DMA & operator=(const DMA &)=delete
A DMA is not assignable.
ComSquare::CPU::DMA::_writeOneByte
unsigned _writeOneByte(uint24_t aAddress, uint24_t bAddress)
Write one byte using the A address, the port and the _direction. Handle special cases where no write ...
Definition: DMA.cpp:71
ComSquare::CPU::DMA
Class handling all DMA/HDMA transfers (Direct Memory Access or H-Blank Direct Memory Access)
Definition: DMA.hpp:19
ComSquare::Memory::IMemoryBus
The memory bus is the component responsible of mapping addresses to components address and transmitti...
Definition: IMemoryBus.hpp:19
ComSquare::CPU::DMA::raw
uint24_t raw
Definition: DMA.hpp:85
ComSquare::CPU::DMA::read
uint8_t read(uint8_t addr) const
Bus helper to read from this channel.
Definition: DMA.cpp:20
ComSquare::CPU::DMA::_getModeOffset
int _getModeOffset(int index) const
Get an offset corresponding to the current DMAMode and the index of the currently transferred byte.
Definition: DMA.cpp:112
ComSquare::CPU::DMA::_bus
Memory::IMemoryBus & _bus
The memory bus to use for read/write.
Definition: DMA.hpp:96
ComSquare::CPU::DMA::_count
union ComSquare::CPU::DMA::@40 _count
The number of bytes to be transferred.
ComSquare::CPU::DMA::bytes
uint8_t bytes[3]
Definition: DMA.hpp:80
ComSquare::CPU::DMA::bank
uint8_t bank
Definition: DMA.hpp:83
ComSquare::CPU::DMA::TwoToTwoBis
@ TwoToTwoBis
Exactly the same as TwoToTwo (not implemented on the SNES so this fallbacks)
Definition: DMA.hpp:36
RegisterViewer.hpp
ComSquare::CPU::DMA::setBus
void setBus(Memory::IMemoryBus &bus)
Set the memory bus used by this CPU.
Definition: DMA.cpp:15
ComSquare::CPU::DMA::FourToTwo
@ FourToTwo
4 byte is transferred to 2 register (write twice)
Definition: DMA.hpp:32
ComSquare::CPU::DMA::AtoB
@ AtoB
Definition: DMA.hpp:45
ComSquare::CPU::DMA::TwoToTwo
@ TwoToTwo
2 byte is transferred to 2 register (write once)
Definition: DMA.hpp:28
ComSquare::CPU::DMA::run
unsigned run(unsigned cycles)
Run the DMA for x cycles.
Definition: DMA.cpp:96
ComSquare::CPU::DMA::_port
uint8_t _port
If this is 'xx', the register accessed will be $21xx.
Definition: DMA.hpp:75
ComSquare::CPU::DMA::getBus
Memory::IMemoryBus & getBus()
Get the memory bus used by this CPU.
Definition: DMA.hpp:100
ComSquare::CPU::DMA::_controlRegister
union ComSquare::CPU::DMA::@38 _controlRegister
DMA Control register (various information about the transfer)
ComSquare::CPU::DMA::raw
uint8_t raw
Definition: DMA.hpp:71
ComSquare::CPU::DMA::TwoToOneBis
@ TwoToOneBis
Exactly the same as TwoToOne (not implemented on the SNES so this fallbacks)
Definition: DMA.hpp:38
ComSquare::CPU::DMA::DMA
DMA(Memory::IMemoryBus &bus)
Create a DMA channel with a given bus.
Definition: DMA.cpp:10
ComSquare::CPU::DMA::_aAddress
union ComSquare::CPU::DMA::@39 _aAddress
The absolute long address of the data from the A bus.
ComSquare::CPU::DMA::write
void write(uint8_t addr, uint8_t data)
Bus helper to write to this channel.
Definition: DMA.cpp:42
ComSquare::CPU::DMA::OneToOne
@ OneToOne
1 byte is transferred to 1 register (write once)
Definition: DMA.hpp:26
ComSquare::CPU::DMA::FourToTwoBis
@ FourToTwoBis
Exactly the same as FourToTwo (not implemented on the SNES so this fallbacks)
Definition: DMA.hpp:40