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12 #ifdef DEBUGGER_ENABLED
114 [[nodiscard]] uint8_t
read(uint8_t addr)
const;
119 void write(uint8_t addr, uint8_t data);
124 unsigned run(
unsigned cycles);
130 DMA(
const DMA &) =
default;
136 #ifdef DEBUGGER_ENABLED
~DMA()=default
A default destructor.
Definition: RegisterViewer.hpp:49
bool fixed
If this flag is set, no increment/decrement will be done.
Definition: DMA.hpp:63
bool _
Two unused bites.
Definition: DMA.hpp:67
uint16_t raw
Definition: DMA.hpp:92
uint16_t page
Definition: DMA.hpp:82
@ FourToFour
4 byte is transferred to 4 register (write once)
Definition: DMA.hpp:34
Direction direction
The direction of the transfer.
Definition: DMA.hpp:69
@ BtoA
Definition: DMA.hpp:46
@ TwoToOne
2 byte is transferred to 1 register (write twice)
Definition: DMA.hpp:30
DMAMode
The first three bytes of the DMA's control register. Used to tell how many bytes/registers there is.
Definition: DMA.hpp:23
bool enabled
Is this channel set to run?
Definition: DMA.hpp:109
bool increment
if this flag is 0: increment. Else: decrement. (The A address)
Definition: DMA.hpp:65
Definition: AddressingModes.cpp:8
DMAMode mode
DMA's mode: how many bytes/registers there is, how many writes...
Definition: DMA.hpp:61
unsigned uint24_t
Definition: Ints.hpp:10
Direction
Definition: DMA.hpp:43
DMA & operator=(const DMA &)=delete
A DMA is not assignable.
unsigned _writeOneByte(uint24_t aAddress, uint24_t bAddress)
Write one byte using the A address, the port and the _direction. Handle special cases where no write ...
Definition: DMA.cpp:71
Class handling all DMA/HDMA transfers (Direct Memory Access or H-Blank Direct Memory Access)
Definition: DMA.hpp:19
The memory bus is the component responsible of mapping addresses to components address and transmitti...
Definition: IMemoryBus.hpp:19
uint24_t raw
Definition: DMA.hpp:85
uint8_t read(uint8_t addr) const
Bus helper to read from this channel.
Definition: DMA.cpp:20
int _getModeOffset(int index) const
Get an offset corresponding to the current DMAMode and the index of the currently transferred byte.
Definition: DMA.cpp:112
Memory::IMemoryBus & _bus
The memory bus to use for read/write.
Definition: DMA.hpp:96
union ComSquare::CPU::DMA::@40 _count
The number of bytes to be transferred.
uint8_t bytes[3]
Definition: DMA.hpp:80
uint8_t bank
Definition: DMA.hpp:83
@ TwoToTwoBis
Exactly the same as TwoToTwo (not implemented on the SNES so this fallbacks)
Definition: DMA.hpp:36
void setBus(Memory::IMemoryBus &bus)
Set the memory bus used by this CPU.
Definition: DMA.cpp:15
@ FourToTwo
4 byte is transferred to 2 register (write twice)
Definition: DMA.hpp:32
@ AtoB
Definition: DMA.hpp:45
@ TwoToTwo
2 byte is transferred to 2 register (write once)
Definition: DMA.hpp:28
unsigned run(unsigned cycles)
Run the DMA for x cycles.
Definition: DMA.cpp:96
uint8_t _port
If this is 'xx', the register accessed will be $21xx.
Definition: DMA.hpp:75
Memory::IMemoryBus & getBus()
Get the memory bus used by this CPU.
Definition: DMA.hpp:100
union ComSquare::CPU::DMA::@38 _controlRegister
DMA Control register (various information about the transfer)
uint8_t raw
Definition: DMA.hpp:71
@ TwoToOneBis
Exactly the same as TwoToOne (not implemented on the SNES so this fallbacks)
Definition: DMA.hpp:38
DMA(Memory::IMemoryBus &bus)
Create a DMA channel with a given bus.
Definition: DMA.cpp:10
union ComSquare::CPU::DMA::@39 _aAddress
The absolute long address of the data from the A bus.
void write(uint8_t addr, uint8_t data)
Bus helper to write to this channel.
Definition: DMA.cpp:42
@ OneToOne
1 byte is transferred to 1 register (write once)
Definition: DMA.hpp:26
@ FourToTwoBis
Exactly the same as FourToTwo (not implemented on the SNES so this fallbacks)
Definition: DMA.hpp:40