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<div id="projectname">ComSquare
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<li class="navelem"><a class="el" href="namespaceComSquare.html">ComSquare</a></li><li class="navelem"><a class="el" href="namespaceComSquare_1_1CPU.html">CPU</a></li><li class="navelem"><a class="el" href="classComSquare_1_1CPU_1_1DMA.html">DMA</a></li> </ul>
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<div class="summary">
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<a href="#pub-types">Public Types</a> |
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<a href="#pub-methods">Public Member Functions</a> |
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<a href="#pub-attribs">Public Attributes</a> |
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<a href="#pri-methods">Private Member Functions</a> |
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<a href="#pri-attribs">Private Attributes</a> |
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<a href="classComSquare_1_1CPU_1_1DMA-members.html">List of all members</a> </div>
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<div class="headertitle">
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<div class="title">ComSquare::CPU::DMA Class Reference</div> </div>
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<p>Class handling all DMA/HDMA transfers (Direct <a class="el" href="namespaceComSquare_1_1Memory.html">Memory</a> Access or H-Blank Direct <a class="el" href="namespaceComSquare_1_1Memory.html">Memory</a> Access)
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<a href="classComSquare_1_1CPU_1_1DMA.html#details">More...</a></p>
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<p><code>#include <<a class="el" href="DMA_8hpp_source.html">DMA.hpp</a>></code></p>
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Collaboration diagram for ComSquare::CPU::DMA:</div>
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<table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-types"></a>
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Public Types</h2></td></tr>
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<tr class="memitem:a09db4b625719ea8c624bc77a6ffcba39"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="classComSquare_1_1CPU_1_1DMA.html#a09db4b625719ea8c624bc77a6ffcba39">DMAMode</a> { <br />
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  <a class="el" href="classComSquare_1_1CPU_1_1DMA.html#a09db4b625719ea8c624bc77a6ffcba39a86a0bca9633a504c13a142e8732d0654">OneToOne</a> = 0b000,
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<a class="el" href="classComSquare_1_1CPU_1_1DMA.html#a09db4b625719ea8c624bc77a6ffcba39a4436f697495cdfb191337a6d4419a555">TwoToTwo</a> = 0b001,
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<a class="el" href="classComSquare_1_1CPU_1_1DMA.html#a09db4b625719ea8c624bc77a6ffcba39aadedb5cc6298170f2ac0714399db9a66">TwoToOne</a> = 0b010,
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<a class="el" href="classComSquare_1_1CPU_1_1DMA.html#a09db4b625719ea8c624bc77a6ffcba39ae8326b4f06978a369f0f2f7174aa447e">FourToTwo</a> = 0b011,
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<br />
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  <a class="el" href="classComSquare_1_1CPU_1_1DMA.html#a09db4b625719ea8c624bc77a6ffcba39a7d518b3bb843763d2587653192708e6d">FourToFour</a> = 0b100,
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<a class="el" href="classComSquare_1_1CPU_1_1DMA.html#a09db4b625719ea8c624bc77a6ffcba39a8b5fc9672d91f39e13f35269e5191db0">TwoToTwoBis</a> = 0b101,
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<a class="el" href="classComSquare_1_1CPU_1_1DMA.html#a09db4b625719ea8c624bc77a6ffcba39a5f0f9487ca32fb33306fb0a60622b775">TwoToOneBis</a> = 0b110,
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<a class="el" href="classComSquare_1_1CPU_1_1DMA.html#a09db4b625719ea8c624bc77a6ffcba39ae110f671ea0a774b3d0219cb199e65eb">FourToTwoBis</a> = 0b111
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<br />
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}</td></tr>
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<tr class="memdesc:a09db4b625719ea8c624bc77a6ffcba39"><td class="mdescLeft"> </td><td class="mdescRight">The first three bytes of the <a class="el" href="classComSquare_1_1CPU_1_1DMA.html" title="Class handling all DMA/HDMA transfers (Direct Memory Access or H-Blank Direct Memory Access)">DMA</a>'s control register. Used to tell how many bytes/registers there is. <a href="classComSquare_1_1CPU_1_1DMA.html#a09db4b625719ea8c624bc77a6ffcba39">More...</a><br /></td></tr>
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<tr class="separator:a09db4b625719ea8c624bc77a6ffcba39"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a34f471a48a9062c44e0260b3686ba06c"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="classComSquare_1_1CPU_1_1DMA.html#a34f471a48a9062c44e0260b3686ba06c">Direction</a> { <a class="el" href="classComSquare_1_1CPU_1_1DMA.html#a34f471a48a9062c44e0260b3686ba06cac68d0326695de61779072fe85f0bbed1">AtoB</a>,
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<a class="el" href="classComSquare_1_1CPU_1_1DMA.html#a34f471a48a9062c44e0260b3686ba06ca90d173a67b57daa0e8cc0e395f691182">BtoA</a>
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}</td></tr>
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<tr class="separator:a34f471a48a9062c44e0260b3686ba06c"><td class="memSeparator" colspan="2"> </td></tr>
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</table><table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-methods"></a>
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Public Member Functions</h2></td></tr>
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<tr class="memitem:a41a3d98b718c3098b7a0858b50d6fd6e"><td class="memItemLeft" align="right" valign="top"><a class="el" href="classComSquare_1_1Memory_1_1IMemoryBus.html">Memory::IMemoryBus</a> & </td><td class="memItemRight" valign="bottom"><a class="el" href="classComSquare_1_1CPU_1_1DMA.html#a41a3d98b718c3098b7a0858b50d6fd6e">getBus</a> ()</td></tr>
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<tr class="memdesc:a41a3d98b718c3098b7a0858b50d6fd6e"><td class="mdescLeft"> </td><td class="mdescRight">Get the memory bus used by this <a class="el" href="classComSquare_1_1CPU_1_1CPU.html" title="The main CPU.">CPU</a>. <a href="classComSquare_1_1CPU_1_1DMA.html#a41a3d98b718c3098b7a0858b50d6fd6e">More...</a><br /></td></tr>
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<tr class="separator:a41a3d98b718c3098b7a0858b50d6fd6e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3f583dff51b42ad8e50bb54fcd14a451"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="classComSquare_1_1CPU_1_1DMA.html#a3f583dff51b42ad8e50bb54fcd14a451">setBus</a> (<a class="el" href="classComSquare_1_1Memory_1_1IMemoryBus.html">Memory::IMemoryBus</a> &bus)</td></tr>
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<tr class="memdesc:a3f583dff51b42ad8e50bb54fcd14a451"><td class="mdescLeft"> </td><td class="mdescRight">Set the memory bus used by this <a class="el" href="classComSquare_1_1CPU_1_1CPU.html" title="The main CPU.">CPU</a>. <a href="classComSquare_1_1CPU_1_1DMA.html#a3f583dff51b42ad8e50bb54fcd14a451">More...</a><br /></td></tr>
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<tr class="separator:a3f583dff51b42ad8e50bb54fcd14a451"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac15ec6b4981e6097e268a9b65be29a4f"><td class="memItemLeft" align="right" valign="top">uint8_t </td><td class="memItemRight" valign="bottom"><a class="el" href="classComSquare_1_1CPU_1_1DMA.html#ac15ec6b4981e6097e268a9b65be29a4f">read</a> (uint8_t addr) const</td></tr>
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<tr class="memdesc:ac15ec6b4981e6097e268a9b65be29a4f"><td class="mdescLeft"> </td><td class="mdescRight">Bus helper to read from this channel. <a href="classComSquare_1_1CPU_1_1DMA.html#ac15ec6b4981e6097e268a9b65be29a4f">More...</a><br /></td></tr>
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<tr class="separator:ac15ec6b4981e6097e268a9b65be29a4f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a83cc22ce83580854ca78088362a2de9d"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="classComSquare_1_1CPU_1_1DMA.html#a83cc22ce83580854ca78088362a2de9d">write</a> (uint8_t addr, uint8_t data)</td></tr>
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<tr class="memdesc:a83cc22ce83580854ca78088362a2de9d"><td class="mdescLeft"> </td><td class="mdescRight">Bus helper to write to this channel. <a href="classComSquare_1_1CPU_1_1DMA.html#a83cc22ce83580854ca78088362a2de9d">More...</a><br /></td></tr>
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<tr class="separator:a83cc22ce83580854ca78088362a2de9d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a33579bc6e0052d0be73a17a32eb8262e"><td class="memItemLeft" align="right" valign="top">unsigned </td><td class="memItemRight" valign="bottom"><a class="el" href="classComSquare_1_1CPU_1_1DMA.html#a33579bc6e0052d0be73a17a32eb8262e">run</a> (unsigned cycles)</td></tr>
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<tr class="memdesc:a33579bc6e0052d0be73a17a32eb8262e"><td class="mdescLeft"> </td><td class="mdescRight">Run the <a class="el" href="classComSquare_1_1CPU_1_1DMA.html" title="Class handling all DMA/HDMA transfers (Direct Memory Access or H-Blank Direct Memory Access)">DMA</a> for x cycles. <a href="classComSquare_1_1CPU_1_1DMA.html#a33579bc6e0052d0be73a17a32eb8262e">More...</a><br /></td></tr>
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<tr class="separator:a33579bc6e0052d0be73a17a32eb8262e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8a9151c3b6318eea50d556ca5eff985a"><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="classComSquare_1_1CPU_1_1DMA.html#a8a9151c3b6318eea50d556ca5eff985a">DMA</a> (<a class="el" href="classComSquare_1_1Memory_1_1IMemoryBus.html">Memory::IMemoryBus</a> &bus)</td></tr>
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<tr class="memdesc:a8a9151c3b6318eea50d556ca5eff985a"><td class="mdescLeft"> </td><td class="mdescRight">Create a <a class="el" href="classComSquare_1_1CPU_1_1DMA.html" title="Class handling all DMA/HDMA transfers (Direct Memory Access or H-Blank Direct Memory Access)">DMA</a> channel with a given bus. <a href="classComSquare_1_1CPU_1_1DMA.html#a8a9151c3b6318eea50d556ca5eff985a">More...</a><br /></td></tr>
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<tr class="separator:a8a9151c3b6318eea50d556ca5eff985a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6cfdffcb9b2011e3b3205262817e27be"><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="classComSquare_1_1CPU_1_1DMA.html#a6cfdffcb9b2011e3b3205262817e27be">DMA</a> (const <a class="el" href="classComSquare_1_1CPU_1_1DMA.html">DMA</a> &)=default</td></tr>
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<tr class="memdesc:a6cfdffcb9b2011e3b3205262817e27be"><td class="mdescLeft"> </td><td class="mdescRight">A <a class="el" href="classComSquare_1_1CPU_1_1DMA.html" title="Class handling all DMA/HDMA transfers (Direct Memory Access or H-Blank Direct Memory Access)">DMA</a> is copy constructable. <a href="classComSquare_1_1CPU_1_1DMA.html#a6cfdffcb9b2011e3b3205262817e27be">More...</a><br /></td></tr>
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<tr class="separator:a6cfdffcb9b2011e3b3205262817e27be"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aca7d4c5b094154f83f1a62e98b5d6a34"><td class="memItemLeft" align="right" valign="top"><a class="el" href="classComSquare_1_1CPU_1_1DMA.html">DMA</a> & </td><td class="memItemRight" valign="bottom"><a class="el" href="classComSquare_1_1CPU_1_1DMA.html#aca7d4c5b094154f83f1a62e98b5d6a34">operator=</a> (const <a class="el" href="classComSquare_1_1CPU_1_1DMA.html">DMA</a> &)=delete</td></tr>
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<tr class="memdesc:aca7d4c5b094154f83f1a62e98b5d6a34"><td class="mdescLeft"> </td><td class="mdescRight">A <a class="el" href="classComSquare_1_1CPU_1_1DMA.html" title="Class handling all DMA/HDMA transfers (Direct Memory Access or H-Blank Direct Memory Access)">DMA</a> is not assignable. <a href="classComSquare_1_1CPU_1_1DMA.html#aca7d4c5b094154f83f1a62e98b5d6a34">More...</a><br /></td></tr>
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<tr class="separator:aca7d4c5b094154f83f1a62e98b5d6a34"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a65aa5e884fa822949d5b7c34b7cec98e"><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="classComSquare_1_1CPU_1_1DMA.html#a65aa5e884fa822949d5b7c34b7cec98e">~DMA</a> ()=default</td></tr>
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<tr class="memdesc:a65aa5e884fa822949d5b7c34b7cec98e"><td class="mdescLeft"> </td><td class="mdescRight">A default destructor. <a href="classComSquare_1_1CPU_1_1DMA.html#a65aa5e884fa822949d5b7c34b7cec98e">More...</a><br /></td></tr>
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<tr class="separator:a65aa5e884fa822949d5b7c34b7cec98e"><td class="memSeparator" colspan="2"> </td></tr>
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</table><table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
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Public Attributes</h2></td></tr>
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<tr class="memitem:a92fbb57324fbdf99e9d97a304c4f2083"><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="classComSquare_1_1CPU_1_1DMA.html#a92fbb57324fbdf99e9d97a304c4f2083">enabled</a></td></tr>
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<tr class="memdesc:a92fbb57324fbdf99e9d97a304c4f2083"><td class="mdescLeft"> </td><td class="mdescRight">Is this channel set to run? <a href="classComSquare_1_1CPU_1_1DMA.html#a92fbb57324fbdf99e9d97a304c4f2083">More...</a><br /></td></tr>
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<tr class="separator:a92fbb57324fbdf99e9d97a304c4f2083"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3c922413f610803ff3775367023b78b4"><td class="memItemLeft" align="right" valign="top"><a class="el" href="classComSquare_1_1CPU_1_1DMA.html#a09db4b625719ea8c624bc77a6ffcba39">DMAMode</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="classComSquare_1_1CPU_1_1DMA.html#a3c922413f610803ff3775367023b78b4">mode</a>: 3</td></tr>
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<tr class="memdesc:a3c922413f610803ff3775367023b78b4"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="classComSquare_1_1CPU_1_1DMA.html" title="Class handling all DMA/HDMA transfers (Direct Memory Access or H-Blank Direct Memory Access)">DMA</a>'s mode: how many bytes/registers there is, how many writes... <a href="classComSquare_1_1CPU_1_1DMA.html#a3c922413f610803ff3775367023b78b4">More...</a><br /></td></tr>
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<tr class="separator:a3c922413f610803ff3775367023b78b4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3f6e8413e03d475a303a9685e9107bdb"><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="classComSquare_1_1CPU_1_1DMA.html#a3f6e8413e03d475a303a9685e9107bdb">fixed</a>: 1</td></tr>
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<tr class="memdesc:a3f6e8413e03d475a303a9685e9107bdb"><td class="mdescLeft"> </td><td class="mdescRight">If this flag is set, no increment/decrement will be done. <a href="classComSquare_1_1CPU_1_1DMA.html#a3f6e8413e03d475a303a9685e9107bdb">More...</a><br /></td></tr>
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<tr class="separator:a3f6e8413e03d475a303a9685e9107bdb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:addb890a9a0331e2c00e291a93346801e"><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="classComSquare_1_1CPU_1_1DMA.html#addb890a9a0331e2c00e291a93346801e">increment</a>: 1</td></tr>
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<tr class="memdesc:addb890a9a0331e2c00e291a93346801e"><td class="mdescLeft"> </td><td class="mdescRight">if this flag is 0: increment. Else: decrement. (The A address) <a href="classComSquare_1_1CPU_1_1DMA.html#addb890a9a0331e2c00e291a93346801e">More...</a><br /></td></tr>
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<tr class="separator:addb890a9a0331e2c00e291a93346801e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3fdcb50a9a2fa0e8c6b572cd7799f2ad"><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="classComSquare_1_1CPU_1_1DMA.html#a3fdcb50a9a2fa0e8c6b572cd7799f2ad">_</a>: 2</td></tr>
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<tr class="memdesc:a3fdcb50a9a2fa0e8c6b572cd7799f2ad"><td class="mdescLeft"> </td><td class="mdescRight">Two unused bites. <a href="classComSquare_1_1CPU_1_1DMA.html#a3fdcb50a9a2fa0e8c6b572cd7799f2ad">More...</a><br /></td></tr>
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<tr class="separator:a3fdcb50a9a2fa0e8c6b572cd7799f2ad"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0b3074ccfd02bf29ede00d79ef78792e"><td class="memItemLeft" align="right" valign="top"><a class="el" href="classComSquare_1_1CPU_1_1DMA.html#a34f471a48a9062c44e0260b3686ba06c">Direction</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="classComSquare_1_1CPU_1_1DMA.html#a0b3074ccfd02bf29ede00d79ef78792e">direction</a>: 1</td></tr>
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<tr class="memdesc:a0b3074ccfd02bf29ede00d79ef78792e"><td class="mdescLeft"> </td><td class="mdescRight">The direction of the transfer. <a href="classComSquare_1_1CPU_1_1DMA.html#a0b3074ccfd02bf29ede00d79ef78792e">More...</a><br /></td></tr>
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<tr class="memitem:a1ea72efaa83b0bb7862f6cc5fd08c69c"><td class="memItemLeft" align="right" valign="top">uint8_t </td><td class="memItemRight" valign="bottom"><a class="el" href="classComSquare_1_1CPU_1_1DMA.html#a1ea72efaa83b0bb7862f6cc5fd08c69c">raw</a></td></tr>
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<tr class="separator:a1ea72efaa83b0bb7862f6cc5fd08c69c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abc28baf74b33a1ab53c3773c84ed9c57"><td class="memItemLeft" align="right" valign="top">uint8_t </td><td class="memItemRight" valign="bottom"><a class="el" href="classComSquare_1_1CPU_1_1DMA.html#abc28baf74b33a1ab53c3773c84ed9c57">bytes</a> [3]</td></tr>
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<tr class="separator:abc28baf74b33a1ab53c3773c84ed9c57"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a26eb7d20d948f133c086de1ca849de68"><td class="memItemLeft" align="right" valign="top">uint16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="classComSquare_1_1CPU_1_1DMA.html#a26eb7d20d948f133c086de1ca849de68">page</a></td></tr>
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<tr class="separator:a26eb7d20d948f133c086de1ca849de68"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a84708ba0a5589a8ca73ed6284d570c04"><td class="memItemLeft" align="right" valign="top">uint8_t </td><td class="memItemRight" valign="bottom"><a class="el" href="classComSquare_1_1CPU_1_1DMA.html#a84708ba0a5589a8ca73ed6284d570c04">bank</a></td></tr>
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<tr class="separator:a84708ba0a5589a8ca73ed6284d570c04"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9d6db87d17373060c5247858adc8d60d"><td class="memItemLeft" align="right" valign="top"><a class="el" href="Ints_8hpp.html#a89f009aaf5d1964a000f44f09fa0bcf8">uint24_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="classComSquare_1_1CPU_1_1DMA.html#a9d6db87d17373060c5247858adc8d60d">raw</a>: 24</td></tr>
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<tr class="separator:a9d6db87d17373060c5247858adc8d60d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af747887faadea7055e7d074612614bc9"><td class="memItemLeft" align="right" valign="top">uint16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="classComSquare_1_1CPU_1_1DMA.html#af747887faadea7055e7d074612614bc9">raw</a></td></tr>
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</table><table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pri-methods"></a>
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Private Member Functions</h2></td></tr>
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<tr class="memitem:af77e48f1a5875defee964724e556a7b4"><td class="memItemLeft" align="right" valign="top">unsigned </td><td class="memItemRight" valign="bottom"><a class="el" href="classComSquare_1_1CPU_1_1DMA.html#af77e48f1a5875defee964724e556a7b4">_writeOneByte</a> (<a class="el" href="Ints_8hpp.html#a89f009aaf5d1964a000f44f09fa0bcf8">uint24_t</a> aAddress, <a class="el" href="Ints_8hpp.html#a89f009aaf5d1964a000f44f09fa0bcf8">uint24_t</a> bAddress)</td></tr>
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<tr class="memdesc:af77e48f1a5875defee964724e556a7b4"><td class="mdescLeft"> </td><td class="mdescRight">Write one byte using the A address, the port and the _direction. Handle special cases where no write occurs. <a href="classComSquare_1_1CPU_1_1DMA.html#af77e48f1a5875defee964724e556a7b4">More...</a><br /></td></tr>
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<tr class="separator:af77e48f1a5875defee964724e556a7b4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a36b2d5c22ea29a65637e250b95558227"><td class="memItemLeft" align="right" valign="top">int </td><td class="memItemRight" valign="bottom"><a class="el" href="classComSquare_1_1CPU_1_1DMA.html#a36b2d5c22ea29a65637e250b95558227">_getModeOffset</a> (int index) const</td></tr>
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<tr class="memdesc:a36b2d5c22ea29a65637e250b95558227"><td class="mdescLeft"> </td><td class="mdescRight">Get an offset corresponding to the current DMAMode and the index of the currently transferred byte. <a href="classComSquare_1_1CPU_1_1DMA.html#a36b2d5c22ea29a65637e250b95558227">More...</a><br /></td></tr>
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<tr class="separator:a36b2d5c22ea29a65637e250b95558227"><td class="memSeparator" colspan="2"> </td></tr>
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</table><table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pri-attribs"></a>
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Private Attributes</h2></td></tr>
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<tr class="memitem:a8cfd7983eca6c568f75fb243196a39d5"><td class="memItemLeft" >union {</td></tr>
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<tr class="memitem:a44f265f4bc92f862f9affe8551456b0c"><td class="memItemLeft" >   struct {</td></tr>
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<tr class="memitem:ad41b762840b557fd3ec17809331cddba"><td class="memItemLeft" >      <a class="el" href="classComSquare_1_1CPU_1_1DMA.html#a09db4b625719ea8c624bc77a6ffcba39">DMAMode</a>   <a class="el" href="classComSquare_1_1CPU_1_1DMA.html#a3c922413f610803ff3775367023b78b4">mode</a>: 3</td></tr>
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<tr class="memdesc:ad41b762840b557fd3ec17809331cddba"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="classComSquare_1_1CPU_1_1DMA.html" title="Class handling all DMA/HDMA transfers (Direct Memory Access or H-Blank Direct Memory Access)">DMA</a>'s mode: how many bytes/registers there is, how many writes... <a href="structComSquare_1_1CPU_1_1DMA_1_1_0d38_1_1_0d41.html#ad41b762840b557fd3ec17809331cddba">More...</a><br /></td></tr>
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<tr class="separator:ad41b762840b557fd3ec17809331cddba"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afb1a8fc173c7480d82414711de7f83ca"><td class="memItemLeft" >      bool   <a class="el" href="classComSquare_1_1CPU_1_1DMA.html#a3f6e8413e03d475a303a9685e9107bdb">fixed</a>: 1</td></tr>
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<tr class="memdesc:afb1a8fc173c7480d82414711de7f83ca"><td class="mdescLeft"> </td><td class="mdescRight">If this flag is set, no increment/decrement will be done. <a href="structComSquare_1_1CPU_1_1DMA_1_1_0d38_1_1_0d41.html#afb1a8fc173c7480d82414711de7f83ca">More...</a><br /></td></tr>
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<tr class="separator:afb1a8fc173c7480d82414711de7f83ca"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a318362328644536f81dd041004639a77"><td class="memItemLeft" >      bool   <a class="el" href="classComSquare_1_1CPU_1_1DMA.html#addb890a9a0331e2c00e291a93346801e">increment</a>: 1</td></tr>
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<tr class="memdesc:a318362328644536f81dd041004639a77"><td class="mdescLeft"> </td><td class="mdescRight">if this flag is 0: increment. Else: decrement. (The A address) <a href="structComSquare_1_1CPU_1_1DMA_1_1_0d38_1_1_0d41.html#a318362328644536f81dd041004639a77">More...</a><br /></td></tr>
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<tr class="separator:a318362328644536f81dd041004639a77"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a10bf60b577f5391c93213e03d3597021"><td class="memItemLeft" >      bool   <a class="el" href="classComSquare_1_1CPU_1_1DMA.html#a3fdcb50a9a2fa0e8c6b572cd7799f2ad">_</a>: 2</td></tr>
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<tr class="memdesc:a10bf60b577f5391c93213e03d3597021"><td class="mdescLeft"> </td><td class="mdescRight">Two unused bites. <a href="structComSquare_1_1CPU_1_1DMA_1_1_0d38_1_1_0d41.html#a10bf60b577f5391c93213e03d3597021">More...</a><br /></td></tr>
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<tr class="separator:a10bf60b577f5391c93213e03d3597021"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abfd07876ea9efebb806452f021df5379"><td class="memItemLeft" >      <a class="el" href="classComSquare_1_1CPU_1_1DMA.html#a34f471a48a9062c44e0260b3686ba06c">Direction</a>   <a class="el" href="classComSquare_1_1CPU_1_1DMA.html#a0b3074ccfd02bf29ede00d79ef78792e">direction</a>: 1</td></tr>
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<tr class="memdesc:abfd07876ea9efebb806452f021df5379"><td class="mdescLeft"> </td><td class="mdescRight">The direction of the transfer. <a href="structComSquare_1_1CPU_1_1DMA_1_1_0d38_1_1_0d41.html#abfd07876ea9efebb806452f021df5379">More...</a><br /></td></tr>
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<tr class="separator:abfd07876ea9efebb806452f021df5379"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a44f265f4bc92f862f9affe8551456b0c"><td class="memItemLeft" valign="top">   } </td><td class="memItemRight" valign="bottom"></td></tr>
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<tr class="separator:a44f265f4bc92f862f9affe8551456b0c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a75199d8a24e6f25aca0580065ee4851a"><td class="memItemLeft" >   uint8_t   <a class="el" href="classComSquare_1_1CPU_1_1DMA.html#a1ea72efaa83b0bb7862f6cc5fd08c69c">raw</a></td></tr>
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<tr class="memitem:a8cfd7983eca6c568f75fb243196a39d5"><td class="memItemLeft" valign="top">} </td><td class="memItemRight" valign="bottom"><a class="el" href="classComSquare_1_1CPU_1_1DMA.html#a8cfd7983eca6c568f75fb243196a39d5">_controlRegister</a></td></tr>
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<tr class="memdesc:a8cfd7983eca6c568f75fb243196a39d5"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="classComSquare_1_1CPU_1_1DMA.html" title="Class handling all DMA/HDMA transfers (Direct Memory Access or H-Blank Direct Memory Access)">DMA</a> Control register (various information about the transfer) <a href="classComSquare_1_1CPU_1_1DMA.html#a8cfd7983eca6c568f75fb243196a39d5">More...</a><br /></td></tr>
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<tr class="separator:a8cfd7983eca6c568f75fb243196a39d5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aec13e71fb0f68dcaa7b34b1cba600995"><td class="memItemLeft" align="right" valign="top">uint8_t </td><td class="memItemRight" valign="bottom"><a class="el" href="classComSquare_1_1CPU_1_1DMA.html#aec13e71fb0f68dcaa7b34b1cba600995">_port</a> {}</td></tr>
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<tr class="memdesc:aec13e71fb0f68dcaa7b34b1cba600995"><td class="mdescLeft"> </td><td class="mdescRight">If this is 'xx', the register accessed will be $21xx. <a href="classComSquare_1_1CPU_1_1DMA.html#aec13e71fb0f68dcaa7b34b1cba600995">More...</a><br /></td></tr>
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<tr class="separator:aec13e71fb0f68dcaa7b34b1cba600995"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a07adc4917067ddecea619a77fb2910f0"><td class="memItemLeft" >union {</td></tr>
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<tr class="memitem:a0b38efdac5cf122c84bb70e2289ea29c"><td class="memItemLeft" >   uint8_t   <a class="el" href="classComSquare_1_1CPU_1_1DMA.html#abc28baf74b33a1ab53c3773c84ed9c57">bytes</a> [3]</td></tr>
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<tr class="separator:a0b38efdac5cf122c84bb70e2289ea29c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2a22badcd425b6d0a35f5aef3fd89f5d"><td class="memItemLeft" >   struct {</td></tr>
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<tr class="memitem:a954897493aa749c79d2e4162e50ab2cc"><td class="memItemLeft" >      uint16_t   <a class="el" href="classComSquare_1_1CPU_1_1DMA.html#a26eb7d20d948f133c086de1ca849de68">page</a></td></tr>
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<tr class="separator:a954897493aa749c79d2e4162e50ab2cc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abd4ac4bfaf478cbc895cc762fe381893"><td class="memItemLeft" >      uint8_t   <a class="el" href="classComSquare_1_1CPU_1_1DMA.html#a84708ba0a5589a8ca73ed6284d570c04">bank</a></td></tr>
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<tr class="memitem:a2a22badcd425b6d0a35f5aef3fd89f5d"><td class="memItemLeft" valign="top">   } </td><td class="memItemRight" valign="bottom"></td></tr>
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<tr class="separator:a2a22badcd425b6d0a35f5aef3fd89f5d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a33b865ec3a83472085da0aafeadf2758"><td class="memItemLeft" >   <a class="el" href="Ints_8hpp.html#a89f009aaf5d1964a000f44f09fa0bcf8">uint24_t</a>   <a class="el" href="classComSquare_1_1CPU_1_1DMA.html#a9d6db87d17373060c5247858adc8d60d">raw</a>: 24</td></tr>
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<tr class="separator:a33b865ec3a83472085da0aafeadf2758"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a07adc4917067ddecea619a77fb2910f0"><td class="memItemLeft" valign="top">} </td><td class="memItemRight" valign="bottom"><a class="el" href="classComSquare_1_1CPU_1_1DMA.html#a07adc4917067ddecea619a77fb2910f0">_aAddress</a></td></tr>
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<tr class="memdesc:a07adc4917067ddecea619a77fb2910f0"><td class="mdescLeft"> </td><td class="mdescRight">The absolute long address of the data from the A bus. <a href="classComSquare_1_1CPU_1_1DMA.html#a07adc4917067ddecea619a77fb2910f0">More...</a><br /></td></tr>
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<tr class="separator:a07adc4917067ddecea619a77fb2910f0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a590b393a8dd0cb07b436af0b65f9fb30"><td class="memItemLeft" >union {</td></tr>
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<tr class="memitem:a9bb63e17124117f2332238e933b6a19e"><td class="memItemLeft" >   uint8_t   <a class="el" href="classComSquare_1_1CPU_1_1DMA.html#abc28baf74b33a1ab53c3773c84ed9c57">bytes</a> [2]</td></tr>
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<tr class="separator:a9bb63e17124117f2332238e933b6a19e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4a09cf4776b73d66dc3f4f4d9ee64dce"><td class="memItemLeft" >   uint16_t   <a class="el" href="classComSquare_1_1CPU_1_1DMA.html#af747887faadea7055e7d074612614bc9">raw</a></td></tr>
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<tr class="separator:a4a09cf4776b73d66dc3f4f4d9ee64dce"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a590b393a8dd0cb07b436af0b65f9fb30"><td class="memItemLeft" valign="top">} </td><td class="memItemRight" valign="bottom"><a class="el" href="classComSquare_1_1CPU_1_1DMA.html#a590b393a8dd0cb07b436af0b65f9fb30">_count</a></td></tr>
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<tr class="memdesc:a590b393a8dd0cb07b436af0b65f9fb30"><td class="mdescLeft"> </td><td class="mdescRight">The number of bytes to be transferred. <a href="classComSquare_1_1CPU_1_1DMA.html#a590b393a8dd0cb07b436af0b65f9fb30">More...</a><br /></td></tr>
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<tr class="separator:a590b393a8dd0cb07b436af0b65f9fb30"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a57b5deee11bcf984d7e2821cfb22b2f8"><td class="memItemLeft" align="right" valign="top"><a class="el" href="classComSquare_1_1Memory_1_1IMemoryBus.html">Memory::IMemoryBus</a> & </td><td class="memItemRight" valign="bottom"><a class="el" href="classComSquare_1_1CPU_1_1DMA.html#a57b5deee11bcf984d7e2821cfb22b2f8">_bus</a></td></tr>
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<tr class="memdesc:a57b5deee11bcf984d7e2821cfb22b2f8"><td class="mdescLeft"> </td><td class="mdescRight">The memory bus to use for read/write. <a href="classComSquare_1_1CPU_1_1DMA.html#a57b5deee11bcf984d7e2821cfb22b2f8">More...</a><br /></td></tr>
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<tr class="separator:a57b5deee11bcf984d7e2821cfb22b2f8"><td class="memSeparator" colspan="2"> </td></tr>
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</table>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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<div class="textblock"><p>Class handling all DMA/HDMA transfers (Direct <a class="el" href="namespaceComSquare_1_1Memory.html">Memory</a> Access or H-Blank Direct <a class="el" href="namespaceComSquare_1_1Memory.html">Memory</a> Access) </p>
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</div><h2 class="groupheader">Member Enumeration Documentation</h2>
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<a id="a34f471a48a9062c44e0260b3686ba06c"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a34f471a48a9062c44e0260b3686ba06c">◆ </a></span>Direction</h2>
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<td class="memname">enum <a class="el" href="classComSquare_1_1CPU_1_1DMA.html#a34f471a48a9062c44e0260b3686ba06c">ComSquare::CPU::DMA::Direction</a></td>
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</div><div class="memdoc">
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<table class="fieldtable">
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<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="a34f471a48a9062c44e0260b3686ba06cac68d0326695de61779072fe85f0bbed1"></a>AtoB </td><td class="fielddoc"></td></tr>
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<tr><td class="fieldname"><a id="a34f471a48a9062c44e0260b3686ba06ca90d173a67b57daa0e8cc0e395f691182"></a>BtoA </td><td class="fielddoc"></td></tr>
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</div>
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<a id="a09db4b625719ea8c624bc77a6ffcba39"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a09db4b625719ea8c624bc77a6ffcba39">◆ </a></span>DMAMode</h2>
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<td class="memname">enum <a class="el" href="classComSquare_1_1CPU_1_1DMA.html#a09db4b625719ea8c624bc77a6ffcba39">ComSquare::CPU::DMA::DMAMode</a></td>
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<p>The first three bytes of the <a class="el" href="classComSquare_1_1CPU_1_1DMA.html" title="Class handling all DMA/HDMA transfers (Direct Memory Access or H-Blank Direct Memory Access)">DMA</a>'s control register. Used to tell how many bytes/registers there is. </p>
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<table class="fieldtable">
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<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="a09db4b625719ea8c624bc77a6ffcba39a86a0bca9633a504c13a142e8732d0654"></a>OneToOne </td><td class="fielddoc"><p>1 byte is transferred to 1 register (write once) </p>
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<tr><td class="fieldname"><a id="a09db4b625719ea8c624bc77a6ffcba39a4436f697495cdfb191337a6d4419a555"></a>TwoToTwo </td><td class="fielddoc"><p>2 byte is transferred to 2 register (write once) </p>
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</td></tr>
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<tr><td class="fieldname"><a id="a09db4b625719ea8c624bc77a6ffcba39aadedb5cc6298170f2ac0714399db9a66"></a>TwoToOne </td><td class="fielddoc"><p>2 byte is transferred to 1 register (write twice) </p>
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<tr><td class="fieldname"><a id="a09db4b625719ea8c624bc77a6ffcba39ae8326b4f06978a369f0f2f7174aa447e"></a>FourToTwo </td><td class="fielddoc"><p>4 byte is transferred to 2 register (write twice) </p>
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<tr><td class="fieldname"><a id="a09db4b625719ea8c624bc77a6ffcba39a7d518b3bb843763d2587653192708e6d"></a>FourToFour </td><td class="fielddoc"><p>4 byte is transferred to 4 register (write once) </p>
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<tr><td class="fieldname"><a id="a09db4b625719ea8c624bc77a6ffcba39a8b5fc9672d91f39e13f35269e5191db0"></a>TwoToTwoBis </td><td class="fielddoc"><p>Exactly the same as TwoToTwo (not implemented on the <a class="el" href="classComSquare_1_1SNES.html" title="Container of all the components of the SNES.">SNES</a> so this fallbacks) </p>
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<tr><td class="fieldname"><a id="a09db4b625719ea8c624bc77a6ffcba39a5f0f9487ca32fb33306fb0a60622b775"></a>TwoToOneBis </td><td class="fielddoc"><p>Exactly the same as TwoToOne (not implemented on the <a class="el" href="classComSquare_1_1SNES.html" title="Container of all the components of the SNES.">SNES</a> so this fallbacks) </p>
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<tr><td class="fieldname"><a id="a09db4b625719ea8c624bc77a6ffcba39ae110f671ea0a774b3d0219cb199e65eb"></a>FourToTwoBis </td><td class="fielddoc"><p>Exactly the same as FourToTwo (not implemented on the <a class="el" href="classComSquare_1_1SNES.html" title="Container of all the components of the SNES.">SNES</a> so this fallbacks) </p>
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<h2 class="groupheader">Constructor & Destructor Documentation</h2>
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<a id="a8a9151c3b6318eea50d556ca5eff985a"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a8a9151c3b6318eea50d556ca5eff985a">◆ </a></span>DMA() <span class="overload">[1/2]</span></h2>
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<td class="paramtype"><a class="el" href="classComSquare_1_1Memory_1_1IMemoryBus.html">Memory::IMemoryBus</a> & </td>
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<p>Create a <a class="el" href="classComSquare_1_1CPU_1_1DMA.html" title="Class handling all DMA/HDMA transfers (Direct Memory Access or H-Blank Direct Memory Access)">DMA</a> channel with a given bus. </p>
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<h2 class="memtitle"><span class="permalink"><a href="#a6cfdffcb9b2011e3b3205262817e27be">◆ </a></span>DMA() <span class="overload">[2/2]</span></h2>
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<td class="paramtype">const <a class="el" href="classComSquare_1_1CPU_1_1DMA.html">DMA</a> & </td>
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<p>A <a class="el" href="classComSquare_1_1CPU_1_1DMA.html" title="Class handling all DMA/HDMA transfers (Direct Memory Access or H-Blank Direct Memory Access)">DMA</a> is copy constructable. </p>
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<h2 class="memtitle"><span class="permalink"><a href="#a65aa5e884fa822949d5b7c34b7cec98e">◆ </a></span>~DMA()</h2>
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<td>(</td>
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<p>A default destructor. </p>
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<h2 class="groupheader">Member Function Documentation</h2>
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<h2 class="memtitle"><span class="permalink"><a href="#a36b2d5c22ea29a65637e250b95558227">◆ </a></span>_getModeOffset()</h2>
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<td class="paramname"><em>index</em></td><td>)</td>
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<p>Get an offset corresponding to the current DMAMode and the index of the currently transferred byte. </p>
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<h2 class="memtitle"><span class="permalink"><a href="#af77e48f1a5875defee964724e556a7b4">◆ </a></span>_writeOneByte()</h2>
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<p>Write one byte using the A address, the port and the _direction. Handle special cases where no write occurs. </p>
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<h2 class="memtitle"><span class="permalink"><a href="#a41a3d98b718c3098b7a0858b50d6fd6e">◆ </a></span>getBus()</h2>
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<td class="memname"><a class="el" href="classComSquare_1_1Memory_1_1IMemoryBus.html">Memory::IMemoryBus</a>& ComSquare::CPU::DMA::getBus </td>
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<p>Get the memory bus used by this <a class="el" href="classComSquare_1_1CPU_1_1CPU.html" title="The main CPU.">CPU</a>. </p>
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<h2 class="memtitle"><span class="permalink"><a href="#aca7d4c5b094154f83f1a62e98b5d6a34">◆ </a></span>operator=()</h2>
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<p>A <a class="el" href="classComSquare_1_1CPU_1_1DMA.html" title="Class handling all DMA/HDMA transfers (Direct Memory Access or H-Blank Direct Memory Access)">DMA</a> is not assignable. </p>
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<h2 class="memtitle"><span class="permalink"><a href="#ac15ec6b4981e6097e268a9b65be29a4f">◆ </a></span>read()</h2>
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<p>Bus helper to read from this channel. </p>
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<h2 class="memtitle"><span class="permalink"><a href="#a33579bc6e0052d0be73a17a32eb8262e">◆ </a></span>run()</h2>
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<p>Run the <a class="el" href="classComSquare_1_1CPU_1_1DMA.html" title="Class handling all DMA/HDMA transfers (Direct Memory Access or H-Blank Direct Memory Access)">DMA</a> for x cycles. </p>
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<p>Set the memory bus used by this <a class="el" href="classComSquare_1_1CPU_1_1CPU.html" title="The main CPU.">CPU</a>. </p>
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<h2 class="memtitle"><span class="permalink"><a href="#a83cc22ce83580854ca78088362a2de9d">◆ </a></span>write()</h2>
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<p>Bus helper to write to this channel. </p>
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<h2 class="groupheader">Member Data Documentation</h2>
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<a id="a3fdcb50a9a2fa0e8c6b572cd7799f2ad"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a3fdcb50a9a2fa0e8c6b572cd7799f2ad">◆ </a></span>_</h2>
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<p>Two unused bites. </p>
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<p>The absolute long address of the data from the A bus. </p>
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<h2 class="memtitle"><span class="permalink"><a href="#a57b5deee11bcf984d7e2821cfb22b2f8">◆ </a></span>_bus</h2>
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<td class="memname"><a class="el" href="classComSquare_1_1Memory_1_1IMemoryBus.html">Memory::IMemoryBus</a>& ComSquare::CPU::DMA::_bus</td>
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<span class="mlabels"><span class="mlabel">private</span></span> </td>
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<p>The memory bus to use for read/write. </p>
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<h2 class="memtitle"><span class="permalink"><a href="#a8cfd7983eca6c568f75fb243196a39d5">◆ </a></span>_controlRegister</h2>
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<td class="memname">union { ... } ComSquare::CPU::DMA::_controlRegister</td>
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<p><a class="el" href="classComSquare_1_1CPU_1_1DMA.html" title="Class handling all DMA/HDMA transfers (Direct Memory Access or H-Blank Direct Memory Access)">DMA</a> Control register (various information about the transfer) </p>
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<td class="memname">union { ... } ComSquare::CPU::DMA::_count</td>
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<p>The number of bytes to be transferred. </p>
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<td class="memname">uint8_t ComSquare::CPU::DMA::_port {}</td>
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<p>If this is 'xx', the register accessed will be $21xx. </p>
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<h2 class="memtitle"><span class="permalink"><a href="#a84708ba0a5589a8ca73ed6284d570c04">◆ </a></span>bank</h2>
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<td class="memname">uint8_t ComSquare::CPU::DMA::bank</td>
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<h2 class="memtitle"><span class="permalink"><a href="#abc28baf74b33a1ab53c3773c84ed9c57">◆ </a></span>bytes</h2>
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<td class="memname">uint8_t ComSquare::CPU::DMA::bytes[2]</td>
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<h2 class="memtitle"><span class="permalink"><a href="#a0b3074ccfd02bf29ede00d79ef78792e">◆ </a></span>direction</h2>
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<td class="memname"><a class="el" href="classComSquare_1_1CPU_1_1DMA.html#a34f471a48a9062c44e0260b3686ba06c">Direction</a> ComSquare::CPU::DMA::direction</td>
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<p>The direction of the transfer. </p>
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<h2 class="memtitle"><span class="permalink"><a href="#a92fbb57324fbdf99e9d97a304c4f2083">◆ </a></span>enabled</h2>
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<td class="memname">bool ComSquare::CPU::DMA::enabled</td>
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<p>Is this channel set to run? </p>
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<p>If this flag is set, no increment/decrement will be done. </p>
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<h2 class="memtitle"><span class="permalink"><a href="#addb890a9a0331e2c00e291a93346801e">◆ </a></span>increment</h2>
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<p>if this flag is 0: increment. Else: decrement. (The A address) </p>
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<h2 class="memtitle"><span class="permalink"><a href="#a3c922413f610803ff3775367023b78b4">◆ </a></span>mode</h2>
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<td class="memname"><a class="el" href="classComSquare_1_1CPU_1_1DMA.html#a09db4b625719ea8c624bc77a6ffcba39">DMAMode</a> ComSquare::CPU::DMA::mode</td>
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<p><a class="el" href="classComSquare_1_1CPU_1_1DMA.html" title="Class handling all DMA/HDMA transfers (Direct Memory Access or H-Blank Direct Memory Access)">DMA</a>'s mode: how many bytes/registers there is, how many writes... </p>
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<td class="memname">uint16_t ComSquare::CPU::DMA::page</td>
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<td class="memname"><a class="el" href="Ints_8hpp.html#a89f009aaf5d1964a000f44f09fa0bcf8">uint24_t</a> ComSquare::CPU::DMA::raw</td>
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<hr/>The documentation for this class was generated from the following files:<ul>
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<li>sources/CPU/DMA/<a class="el" href="DMA_8hpp_source.html">DMA.hpp</a></li>
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<li>sources/CPU/DMA/<a class="el" href="DMA_8cpp.html">DMA.cpp</a></li>
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