33 Commits

Author SHA1 Message Date
069da6fa90 Use reflow for mc 2025-11-07 18:10:53 +01:00
7ad4d522a9 Fix resetbtn & bat conn 2025-11-07 14:38:16 +01:00
ce44e5535e Fix case 2025-11-04 12:16:36 +01:00
db3ae93136 Add pcb tri jumper for reset 2025-11-04 12:05:09 +01:00
f6cdff3275 wip: Battery and mc fixes 2025-10-29 12:03:52 +01:00
580c303440 wip: Battery and mc fixes 2025-10-29 01:16:10 +01:00
6554d4369f Fix rst btn 2025-10-26 23:55:27 +01:00
1da2eb3048 Cleanup mc hole & magnet holes 2025-10-26 22:45:16 +01:00
86212438e8 Fix magnets in case 2025-09-22 18:07:39 +02:00
b6ffeca3fe Fix holes in top 2025-09-21 17:20:27 +02:00
Quentin Joly
67fd67428f Fix key position 2025-09-21 14:46:49 +02:00
f12c65aa15 . 2025-09-20 18:46:00 +02:00
0bd586b7d3 Fix usb hole placement 2025-09-20 18:11:59 +02:00
2e2b362e11 . 2025-09-20 17:01:02 +02:00
88c17431e4 Fix case size 2025-09-20 16:27:35 +02:00
caa979eea5 Fix m2 holes and standoff 2025-09-20 15:46:15 +02:00
3553378a29 Angle slit 2025-09-18 17:35:07 +02:00
6ca20e87e7 Fix magnet hole placements 2025-09-18 17:34:38 +02:00
4a31619614 Fix some case issues 2025-09-18 14:10:25 +02:00
25a6a61606 Finish pcb 2025-09-04 11:45:10 +02:00
a2f4ab6a17 Fix warnings 2025-09-03 18:39:28 +02:00
ae58943461 Add tri jumper 2025-09-03 18:10:53 +02:00
fedcacb8e1 wip 2025-09-03 12:05:43 +02:00
d33836f8ed Move m2 holes in bottom lid 2025-09-01 15:05:50 +02:00
0bde732e80 Add second m2 standoff 2025-09-01 14:15:06 +02:00
bc2becb226 Remake m2 standoff holes 2025-09-01 12:13:36 +02:00
41808eb30d Cleanup material list 2025-09-01 00:55:30 +02:00
3c542fae19 wip: Add stand magnets holes 2025-08-31 23:47:27 +02:00
0c4da3232c Center magnet in case stand 2025-08-31 23:26:10 +02:00
18c2d11309 Move magnets in case 2025-08-31 22:56:53 +02:00
a494570c97 Move magnets 2025-08-31 22:37:34 +02:00
f502de9845 Remove usb cutout 2025-08-31 19:38:27 +02:00
1ed8bc3c14 Route everything 2025-08-31 19:19:04 +02:00
8 changed files with 6174 additions and 1741 deletions

View File

@@ -4,16 +4,32 @@ A 32 key split keyboard with a low pinky column.
## Components
- 2x - [Seed Xiao nRF54L15 - mcu](https://www.seeedstudio.com/XIAO-nRF54L15-p-6493.html)
- 2x - [1208YD - reset button - 6x6x7mm](https://fr.aliexpress.com/item/1005003938985112.html?spm=a2g0o.order_list.order_list_main.5.21ef1802F8o6h5&gatewayAdapt=glo2fra)
- 2x - [401030 Li-Po Batter - 4x10x30mm battery](https://www.ebay.com/itm/171812433827)
- 16x - 3x6mm magnets
- 16x - ??mm m2 screws
- 4x - ??mm m2 inserts
| Count | Part name | Size/Remark |
| :---: | :-------------- | :------ |
| 2x | [Seed Xiao nRF54L15 - mcu](https://www.seeedstudio.com/XIAO-nRF54L15-p-6493.html) | |
| 2x | [1208YD - reset button](https://fr.aliexpress.com/item/1005003938985112.html?spm=a2g0o.order_list.order_list_main.5.21ef1802F8o6h5&gatewayAdapt=glo2fra) | 6x6x7mm |
| 2x | [401030 Li-Po Battery](https://www.ebay.com/itm/171812433827) | 4x10x30mm |
| 2x | [SM02B-SRSS-TB - battery connector](https://www.jst-mfg.com/product/pdf/eng/eSH.pdf) | |
| 32x | choc switch | i use [sunsets](https://lowprokb.ca/products/sunset-tactile-choc-switches) |
| 30x | 1u choc keycaps | i use [pom](https://splitkb.com/products/moergo-pom-mbk-profile-keycaps?variant=42898367152387) |
| 2x | 1.5u choc keycaps | i use [pom](https://splitkb.com/products/moergo-pom-mbk-profile-keycaps?variant=42898363121923) |
| 32x | [hotswap chock sockets](https://chosfox.com/products/kailh-choc-switch-1350-hot-swap-sockets?_pos=1&_sid=94423b5bb&_ss=r) | |
| 32x | diodes | |
| 24x | magnets | [1x6mm](https://www.aliexpress.us/item/3256809531283174.html?spm=a2g0o.productlist.main.4.40ba51212c0Deo&aem_p4p_detail=202509010522466451792268114080006371275&algo_pvid=7e6d70c3-9fac-491e-ad4b-6f626d5bf2e2&algo_exp_id=7e6d70c3-9fac-491e-ad4b-6f626d5bf2e2-3&pdp_ext_f=%7B%22order%22%3A%221%22%2C%22eval%22%3A%221%22%7D&pdp_npi=6%40dis%21USD%214.46%213.21%21%21%214.46%213.21%21%402103868817567293667515955e9050%2112000049939869309%21sea%21US%210%21ABX%211%210%21n_tag%3A-29910%3Bd%3A8c8b81cd%3Bm03_new_user%3A-29895&curPageLogUid=1SsSuJ8YjbqV&utparam-url=scene%3Asearch%7Cquery_from%3A%7Cx_object_id%3A1005009717597926%7C_p_origin_prod%3A&search_p4p_id=202509010522466451792268114080006371275_1) |
| 4x | m2 screws | 4/6/8mm |
| 4x | m2 standoff | [<5mm wide, 6mm height](https://www.aliexpress.us/item/3256804230166399.html?spm=a2g0o.productlist.main.6.3a56Op21Op215V&algo_pvid=0788da77-fa40-49b3-9d72-f4cf68a2b90f&algo_exp_id=0788da77-fa40-49b3-9d72-f4cf68a2b90f-5&pdp_ext_f=%7B%22order%22%3A%22229%22%2C%22eval%22%3A%221%22%7D&pdp_npi=6%40dis%21USD%212.35%210.99%21%21%212.35%210.99%21%40211b655217567292930196247e11b4%2112000029108517137%21sea%21US%210%21ABX%211%210%21n_tag%3A-29910%3Bd%3A8c8b81cd%3Bm03_new_user%3A-29895%3BpisId%3A5000000174221208&curPageLogUid=uw39hgxJul2o&utparam-url=scene%3Asearch%7Cquery_from%3A%7Cx_object_id%3A1005004416481151%7C_p_origin_prod%3A#nav-description)|
## Info
Case height: 1.6mm (pcb) + 3.1mm (hotswap socket) + 5.5mm (choc size on top of the pcb)
Case dimensions:
- height: 10.5mm -> 1.6mm (pcb) + 3.1mm (hotswap socket) + 5.5mm (choc size on top of the pcb)
- length: 115.38mm
- width: 96.25mm
Transport case dimesions:
- height: 30mm (2x2mm for enclosure, 2x10.5mm for keyboard, 5mm in middle for keycaps + gap)
- length: 124.35mm
- width: 105.25mm
## Keymap

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View File

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133
pcb/abyss.kicad_dru Normal file
View File

@@ -0,0 +1,133 @@
(version 1)
# Custom Design Rules (DRC) for KiCAD 7.0 (Stored in '<project>.kicad_dru' file).
#
# Matching JLCPCB capabilities: https://jlcpcb.com/capabilities/pcb-capabilities
#
# KiCad documentation: https://docs.kicad.org/master/id/pcbnew/pcbnew_advanced.html#custom_design_rules
#
# Inspiration
# - https://gist.github.com/darkxst/f713268e5469645425eed40115fb8b49 (with comments)
# - https://gist.github.com/denniskupec/e163d13b0a64c2044bd259f64659485e (with comments)
# TODO new rule: NPTH pads.
# Inner diameter of pad should be 0.4-0.5 mm larger than NPTH drill diameter.
# JLCPCB: "We make NPTH via dry sealing film process, if customer would like a NPTH but around with pad/copper, our engineer will dig out around pad/copper about 0.2mm-0.25mm, otherwise the metal potion will be flowed into the hole and it becomes a PTH. (there will be no copper dig out optimization for single board)."
# TODO: new rule for plated slots: min diameter/width 0.5mm
# JLCPCB: "The minimum plated slot width is 0.5mm, which is drawn with a pad."
# TODO new rule: non-plated slots: min diameter/width 1.0mm
# JLCPCB: "The minimum Non-Plated Slot Width is 1.0mm, please draw the slot outline in the mechanical layer(GML or GKO)""
(rule "Track width, outer layer (1oz copper)"
(layer outer)
(condition "A.Type == 'track'")
(constraint track_width (min 0.127mm))
)
(rule "Track spacing, outer layer (1oz copper)"
(layer outer)
(condition "A.Type == 'track' && B.Type == A.Type")
(constraint clearance (min 0.127mm))
)
(rule "Track width, inner layer"
(layer inner)
(condition "A.Type == 'track'")
(constraint track_width (min 0.09mm))
)
(rule "Track spacing, inner layer"
(layer inner)
(condition "A.Type == 'track' && B.Type == A.Type")
(constraint clearance (min 0.09mm))
)
(rule "Silkscreen text"
(layer "?.Silkscreen")
(condition "A.Type == 'Text' || A.Type == 'Text Box'")
(constraint text_thickness (min 0.15mm))
(constraint text_height (min 1mm))
)
(rule "Pad to Silkscreen"
(layer outer)
(condition "A.Type == 'pad' && B.Layer == '?.Silkscreen'")
(constraint silk_clearance (min 0.15mm))
)
(rule "Edge (routed) to track clearance"
(condition "A.Type == 'track'")
(constraint edge_clearance (min 0.3mm))
)
#(rule "Edge (v-cut) to track clearance"
# (condition "A.Type == 'track'")
# (constraint edge_clearance (min 0.4mm))
#)
# JLCPCB restrictions ambiguous:
# Illustration: 0.2 mm, 1&2 layer: 0.3 mm, multilayer: "(0.15mm more costly)"
# This rule handles diameter minimum and maximum for ALL holes.
# Other specialized rules handle restrictions (e.g. Via, PTH, NPTH)
(rule "Hole diameter"
(constraint hole_size (min 0.2mm) (max 6.3mm))
)
(rule "Hole (NPTH) diameter"
(layer outer)
(condition "!A.isPlated()")
(constraint hole_size (min 0.5mm))
)
# TODO: Hole to board edge ≥ 1 mm. Min. board size 10 × 10 mm
(rule "Hole (castellated) diameter"
(layer outer)
(condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'")
(constraint hole_size (min 0.6mm))
)
# JLCPCB: "Via diameter should be 0.1mm(0.15mm preferred) larger than Via hole size" (illustration shows diameters for both dimensions)
# JLCPCB: PTH: "The annular ring size will be enlarged to 0.15mm in production."
(rule "Annular ring width (via and PTH)"
(layer outer)
(condition "A.isPlated()")
(constraint annular_width (min 0.075mm))
)
(rule "Clearance: hole to hole (perimeter), different nets"
(layer outer)
(condition "A.Net != B.Net")
(constraint hole_to_hole (min 0.5mm))
)
(rule "Clearance: hole to hole (perimeter), same net"
(layer outer)
(condition "A.Net == B.Net")
(constraint hole_to_hole (min 0.254mm))
)
(rule "Clearance: track to NPTH hole (perimeter)"
# (condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track' && A.Net != B.Net")
(condition "!A.isPlated() && B.Type == 'track' && A.Net != B.Net")
(constraint hole_clearance (min 0.254mm))
)
(rule "Clearance: track to PTH hole perimeter"
(condition "A.isPlated() && B.Type == 'track' && A.Net != B.Net")
(constraint hole_clearance (min 0.33mm))
)
# TODO: try combining with rule "Clearance: PTH to track, different nets"
(rule "Clearance: track to pad"
(condition "A.Type == 'pad' && B.Type == 'track' && A.Net != B.Net")
(constraint clearance (min 0.2mm))
)
(rule "Clearance: pad/via to pad/via"
(layer outer)
# (condition "(A.Type == 'Pad' || A.Type == 'Via') && (B.Type == 'Pad' || B.Type == 'Via') && A.Net != B.Net")
(condition "A.isPlated() && B.isPlated() && A.Net != B.Net")
(constraint clearance (min 0.127mm))
)

File diff suppressed because it is too large Load Diff

View File

@@ -37,9 +37,9 @@
"other_text_thickness": 0.15,
"other_text_upright": false,
"pads": {
"drill": 0.0,
"height": 1.5,
"width": 1.5
"drill": 1.0,
"height": 3.0,
"width": 2.0
},
"silk_line_width": 0.12,
"silk_text_italic": false,
@@ -118,7 +118,7 @@
},
"rules": {
"max_error": 0.005,
"min_clearance": 0.0,
"min_clearance": 0.2,
"min_connection": 0.0,
"min_copper_edge_clearance": 0.075,
"min_groove_width": 0.0,
@@ -226,226 +226,6 @@
"cvpcb": {
"equivalence_files": []
},
"erc": {
"erc_exclusions": [],
"meta": {
"version": 0
},
"pin_map": [
[
0,
0,
0,
0,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
2,
0,
1,
0,
0,
1,
0,
2,
2,
2,
2
],
[
0,
0,
0,
0,
0,
0,
1,
0,
1,
0,
1,
2
],
[
0,
1,
0,
0,
0,
0,
1,
1,
2,
1,
1,
2
],
[
0,
0,
0,
0,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
2
],
[
1,
1,
1,
1,
1,
0,
1,
1,
1,
1,
1,
2
],
[
0,
0,
0,
1,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
2,
1,
2,
0,
0,
1,
0,
2,
2,
2,
2
],
[
0,
2,
0,
1,
0,
0,
1,
0,
2,
0,
0,
2
],
[
0,
2,
1,
1,
0,
0,
1,
0,
2,
0,
0,
2
],
[
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2
]
],
"rule_severities": {
"bus_definition_conflict": "error",
"bus_entry_needed": "error",
"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
"different_unit_footprint": "error",
"different_unit_net": "error",
"duplicate_reference": "error",
"duplicate_sheet_names": "error",
"endpoint_off_grid": "warning",
"extra_units": "error",
"footprint_filter": "ignore",
"footprint_link_issues": "warning",
"four_way_junction": "ignore",
"global_label_dangling": "warning",
"hier_label_mismatch": "error",
"label_dangling": "error",
"label_multiple_wires": "warning",
"lib_symbol_issues": "warning",
"lib_symbol_mismatch": "warning",
"missing_bidi_pin": "warning",
"missing_input_pin": "warning",
"missing_power_pin": "error",
"missing_unit": "warning",
"multiple_net_names": "warning",
"net_not_bus_member": "warning",
"no_connect_connected": "warning",
"no_connect_dangling": "warning",
"pin_not_connected": "error",
"pin_not_driven": "error",
"pin_to_pin": "warning",
"power_pin_not_driven": "error",
"same_local_global_label": "warning",
"similar_label_and_power": "warning",
"similar_labels": "warning",
"similar_power": "warning",
"simulation_model_issue": "ignore",
"single_global_label": "ignore",
"unannotated": "error",
"unconnected_wire_endpoint": "warning",
"unit_value_mismatch": "error",
"unresolved_variable": "error",
"wire_dangling": "error"
}
},
"libraries": {
"pinned_footprint_libs": [],
"pinned_symbol_libs": []
@@ -612,127 +392,18 @@
"gencad": "",
"idf": "",
"netlist": "",
"plot": "",
"plot": "out/",
"pos_files": "",
"specctra_dsn": "",
"step": "",
"step": "abyss.stl",
"svg": "",
"vrml": ""
},
"page_layout_descr_file": ""
},
"schematic": {
"annotate_start_num": 0,
"bom_export_filename": "${PROJECTNAME}.csv",
"bom_fmt_presets": [],
"bom_fmt_settings": {
"field_delimiter": ",",
"keep_line_breaks": false,
"keep_tabs": false,
"name": "CSV",
"ref_delimiter": ",",
"ref_range_delimiter": "",
"string_delimiter": "\""
},
"bom_presets": [],
"bom_settings": {
"exclude_dnp": false,
"fields_ordered": [
{
"group_by": false,
"label": "Reference",
"name": "Reference",
"show": true
},
{
"group_by": false,
"label": "Qty",
"name": "${QUANTITY}",
"show": true
},
{
"group_by": true,
"label": "Value",
"name": "Value",
"show": true
},
{
"group_by": true,
"label": "DNP",
"name": "${DNP}",
"show": true
},
{
"group_by": true,
"label": "Exclude from BOM",
"name": "${EXCLUDE_FROM_BOM}",
"show": true
},
{
"group_by": true,
"label": "Exclude from Board",
"name": "${EXCLUDE_FROM_BOARD}",
"show": true
},
{
"group_by": true,
"label": "Footprint",
"name": "Footprint",
"show": true
},
{
"group_by": false,
"label": "Datasheet",
"name": "Datasheet",
"show": true
}
],
"filter_string": "",
"group_symbols": true,
"include_excluded_from_bom": true,
"name": "Default Editing",
"sort_asc": true,
"sort_field": "Reference"
},
"connection_grid_size": 50.0,
"drawing": {
"dashed_lines_dash_length_ratio": 12.0,
"dashed_lines_gap_length_ratio": 3.0,
"default_line_thickness": 6.0,
"default_text_size": 50.0,
"field_names": [],
"intersheets_ref_own_page": false,
"intersheets_ref_prefix": "",
"intersheets_ref_short": false,
"intersheets_ref_show": false,
"intersheets_ref_suffix": "",
"junction_size_choice": 3,
"label_size_ratio": 0.375,
"operating_point_overlay_i_precision": 3,
"operating_point_overlay_i_range": "~A",
"operating_point_overlay_v_precision": 3,
"operating_point_overlay_v_range": "~V",
"overbar_offset_ratio": 1.23,
"pin_symbol_size": 25.0,
"text_offset_ratio": 0.15
},
"legacy_lib_dir": "",
"legacy_lib_list": [],
"meta": {
"version": 1
},
"net_format_name": "",
"page_layout_descr_file": "",
"plot_directory": "",
"space_save_all_events": true,
"spice_current_sheet_as_root": false,
"spice_external_command": "spice \"%I\"",
"spice_model_current_sheet_as_root": true,
"spice_save_all_currents": false,
"spice_save_all_dissipations": false,
"spice_save_all_voltages": false,
"subpart_first_id": 65,
"subpart_id_separator": 0
"legacy_lib_list": []
},
"sheets": [],
"text_variables": {}